DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 643
DF2148RTE20IV
Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148RTE20IV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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18.3.2
Table 18.5 shows host interface operations from the HIF host, and slave operation.
Table 18.5 Host Interface Operations from HIF Host, and Slave Operation
Note: n = 1 to 4
18.3.3
The A20 gate signal can mask address A20 to emulate an addressing mode used by personal
computers with an 8086 * -family CPU. In slave mode, a regular-speed A20 gate signal can be
output under firmware control. Fast A20 gate output is enabled by setting the FGA20E bit (bit 0)
to 1 in HICR (H'FFF0).
Note: * Intel microprocessor.
Regular A20 Gate Operation
Output of the A20 gate signal can be controlled by an H'D1 command followed by data. When the
slave processor receives data, it normally uses an interrupt routine activated by the IBF1 interrupt
to read IDR1. If the data follows an H'D1 command, software copies bit 1 of the data and outputs
it at the gate A20 pin.
Fast A20 Gate Operation
When the FGA20E bit is set to 1, P81/GA20 is used for output of a fast A20 gate signal. Bit
P81DDR must be set to 1 to assign this pin for output. The initial output from this pin will be a
logic 1, which is the initial value. Afterward, the host processor can manipulate the output from
Other than
CSn
CSn
CSn
CSn
1
Control States
A20 Gate
CSn
CSn
CSn
CSn
0
IOR
IOR
0
1
IOR
IOR
IOW
IOW
0
1
0
1
IOW
IOW
HA0
0
1
0
1
0
1
0
1
Operation
Setting prohibited
Setting prohibited
Data read from output data register n (ODRn)
Status read from status register n (STRn)
Data written to input data register n (IDRn)
Command written to input data register n (IDRn)
Idle state
Idle state
Rev. 4.00 Sep 27, 2006 page 597 of 1130
Section 18 Host Interface
REJ09B0327-0400
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