DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 597
DF2148RTE20IV
Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148RTE20IV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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SDA
SCL
TRS
Notes on ICDR Reads and ICCR Access in Slave Transmit Mode
In a transmit operation in the slave mode of the I
or read or write to the ICCR register during the period indicated by the shaded portion in figure
16.22.
Normally, when interrupt processing is triggered in synchronization with the rising edge of the
9th clock cycle, the period in question has already elapsed when the transition to interrupt
processing takes place, so there is no problem with reading the ICDR register or reading or
writing to the ICCR register.
To ensure that the interrupt processing is performed properly, one of the following two
conditions should be applied.
(1) Make sure that reading received data from the ICDR register, or reading or writing to the
(2) Monitor the BC2 to BC0 counter in the ICMR register and, when the value of BC2 to BC0
ICCR register, is completed before the next slave address receive operation starts.
is 000 (8th or 9th clock cycle), allow a waiting time of at least 2 transfer clock cycles in
order to involve the problem period in question before reading from the ICDR register, or
reading or writing to the ICCR register.
Figure 16.22 ICDR Read and ICCR Access Timing in Slave Transmit Mode
Address received
R/W
8
Detection of 9th clock
cycle rising edge
A
9
Period when ICDR reads and ICCR
reads and writes are prohibited
(6 system clock cycles)
Waveforms if
problem occurs
2
C bus interface, do not read the ICDR register
Rev. 4.00 Sep 27, 2006 page 551 of 1130
Section 16 I
2
C Bus Interface [Option]
Data transmission
REJ09B0327-0400
Bit 7
ICDR write
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