DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 24
DF2148RTE20IV
Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148RTE20IV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Rev. 4.00 Sep 27, 2006 page xxii of xliv
Item
B.3 Functions
Page
1013
1016
1019
1021
ABRKCR H'FEF4 Interrupt Controller
Revision (See Manual for Details)
Subheading amended
KBCOMP H'FEE4 IrDA/Expansion A/D
ISR H'FEEB Interrupt Controller
Figure amended
IRQ7 to IRQ0 flags
Note: * When a product, in which a DTC is incorporated, is
used in the following settings, the corresponding flag bit is not
automatically cleared even when exception handling, which is a
clear condition, is executed and the bit is held at 1.
(1) When DTCEA3 is set to 1 (ADI is set to an interrupt source),
IRQ4F flag is not automatically cleared.
(2) When DTCEA2 is set to 1 (ICIA is set to an interrupt
source), IRQ5F flag is not automatically cleared.
(3) When DTCEA1 is set to 1 (ICIB is set to an interrupt
source), IRQ6F flag is not automatically cleared.
(4) When DTCEA0 is set to 1 (OCIA is set to an interrupt
source), IRQ7F flag is not automatically cleared.
When activation interrupt sources of DTC and IRQ interrupts
are used with the above combinations, clear the interrupt flag
by software in the interrupt handling routine of the
corresponding IRQ.
Read/Write description amended
Bit 7 (Before) R/W
FLMCR1 H'FF80 Flash Memory
Initial value description amended
Bit 7 (Before)
0
[Clearing conditions]
• Cleared by reading IRQnF when set to 1, then writing 0 in IRQnF
• When interrupt exception handling is executed while low-level detection
• When IRQn interrupt exception handling is executed while falling, rising,
is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high *
or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1) *
(After) 1
(After) R
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