DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 233

MCU 5V 128K I-TEMP,PB-FREE, 100-

DF2148RTE20IV

Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148RTE20IV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
7.2.7
The DTC enable registers comprise five 8-bit readable/writable registers, DTCERA to DTCERE,
with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or
disable DTC service for the corresponding interrupt sources.
The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.
Bit n—DTC Activation Enable (DTCEn)
Note: n = 7 to 0
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence
between interrupt sources and DTCE bits is shown in table 7.4, together with the vector number
generated by the interrupt controller in each case.
For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions
such as BSET and BCLR. For the initial setting only, however, when multiple activation sources
are set at one time, it is possible to disable interrupts and write after executing a dummy read on
the relevant register.
Bit n
DTCEn
0
1
Bit
Initial value
Read/Write
DTC Enable Registers (DTCER)
Description
DTC activation by interrupt is disabled
[Clearing conditions]
DTC activation by interrupt is enabled
[Holding condition]
When the DISEL bit is 0 and the specified number of transfers have not ended
When data transfer ends with the DISEL bit set to 1
When the specified number of transfers end
DTCE7
R/W
7
0
DTCE6
R/W
6
0
DTCE5
R/W
5
0
DTCE4
R/W
4
0
Rev. 4.00 Sep 27, 2006 page 187 of 1130
Section 7 Data Transfer Controller (DTC)
DTCE3
R/W
3
0
DTCE2
R/W
2
0
DTCE1
R/W
REJ09B0327-0400
1
0
(Initial value)
DTCE0
R/W
0
0

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