DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 758
DF2148RTE20IV
Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148RTE20IV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 23 ROM
Rev. 4.00 Sep 27, 2006 page 712 of 1130
REJ09B0327-0400
Notes: 1. Preprogramming (setting erase block data to all 0) is not necessary.
2. Verify data is read in 16-bit (W) units.
3. Set only one bit in EBR1or EBR2. More than one bit cannot be set.
4. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially.
5. See
Figure 23.13 Erase/Erase-Verify Flowchart (Single-Block Erase)
(H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Increment
address
section 26.2.6,
NG
NG
Set block start address to verify address
H'FF dummy write to verify address
Flash Memory Characteristics, for the values of x, y, z, , , , , , , and N.
*
Clear ESU bit in FLMCR2
Clear SWE bit in FLMCR1
Set SWE bit in FLMCR1
4
Set ESU bit in FLMCR2
Clear EV bit in FLMCR1
Clear E bit in FLMCR1
Set EV bit in FLMCR1
Last address of block?
Set E bit in FLMCR1
erasing of all erase
Verify data = all 1?
Set EBR1, EBR2
Read verify data
End of erasing
Disable WDT
Enable WDT
Wait (z) ms
Wait (x) s
Wait (y) s
Wait ( ) s
Wait ( ) s
Wait ( ) s
Wait ( ) s
Wait ( ) s
Wait ( ) s
blocks?
End of
n = 1
Start
OK
OK
OK
*
1
*
5
NG
*
*
*
Start of erase
*
Halt erase
*
*
*
*
*
5
3
5
5
5
5
5
5
2
Clear SWE bit in FLMCR1
Clear EV bit in FLMCR1
Erase failure
Wait ( ) s
Wait ( ) s
n
N?
OK
*
5
NG
*
5
n
n + 1
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