DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 122
![MCU 5V 128K I-TEMP,PB-FREE, 100-](/photos/28/61/286108/100-tqfp_sml.jpg)
DF2148RTE20IV
Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148RTE20IV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 2 CPU
Interrupt Exception Handling and Trap Instruction Exception Handling
When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer
(ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU
alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start
address (vector) from the exception vector table and program execution starts from that start
address.
Figure 2.16 shows the stack after exception handling ends.
2.8.4
In this state the CPU executes program instructions in sequence.
2.8.5
This is a state in which the bus has been released in response to a bus request from a bus master
other than the CPU. While the bus is released, all CPU internal operations are halted.
There is one other bus master in addition to the CPU: the data transfer controller (DTC).
For further details, refer to section 6, Bus Controller.
Rev. 4.00 Sep 27, 2006 page 76 of 1130
REJ09B0327-0400
Normal mode
Note: * Ignored when returning.
SP
Program Execution State
Bus-Released State
Figure 2.16 Stack Structure after Exception Handling (Examples)
(16 bits)
CCR
CCR *
PC
Advanced mode
SP
(24 bits)
CCR
PC
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