DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 555
DF2148RTE20IV
Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148RTE20IV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Bit 1
IRIC
0
1
Description
Waiting for transfer, or transfer in progress
[Clearing conditions]
1. When 0 is written in IRIC after reading IRIC = 1
2. When ICDR is written or read by the DTC
Interrupt requested
[Setting conditions]
•
•
•
Except the above, when the conditions to set the TDRE or RDRF internal flag to 1 is generated
(When the TDRE or RDRF flag is cleared to 0)
(This is not always a clearing condition; see the description of DTC operation for details)
I
1. When a start condition is detected in the bus line state after a start condition is issued
2. When a wait is inserted between the data and acknowledge bit when WAIT = 1
3. At the end of data transfer
4. When a slave address is received after bus arbitration is lost
5. When 1 is received as the acknowledge bit when the ACKE bit is 1
I
1. When the slave address (SVA, SVAX) matches
2. When the general call address is detected
3. When 1 is received as the acknowledge bit when the ACKE bit is 1
4. When a stop condition is detected
Synchronous serial format, and formatless mode
1. At the end of data transfer
2. When a start condition is detected with serial format selected
3. When the SW bit is set to 1 in DDCSWR
2
2
C bus format master mode
C bus format slave mode
(when the TDRE flag is set to 1 because of first frame transmission)
(at the rise of the 9th transmit/receive clock pulse when no wait is inserted, (WAIT=0) and,
when a wait is inserted (WAIT=1), at the fall of the 8th transmit/receive clock pulse)
(when the AL flag is set to 1)
(when the ACKB bit is set to 1)
(when the AAS and AASX flags are set to 1)
and at the end of data transfer up to the subsequent retransmission start condition or stop
condition detection
(when the TDRE or RDRF flag is set to 1)
(when FS = 0 and the ADZ flag is set to 1)
and at the end of data transfer up to the subsequent retransmission start condition or stop
condition detection
(when the TDRE or RDRF flag is set to 1)
(when the ACKB bit is set to 1)
(when the STOP or ESTP flag is set to 1)
(when the TDRE or RDRF flag is set to 1)
Rev. 4.00 Sep 27, 2006 page 509 of 1130
Section 16 I
2
C Bus Interface [Option]
REJ09B0327-0400
(Initial value)
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