DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 149
DF2148RTE20IV
Manufacturer Part Number
DF2148RTE20IV
Description
MCU 5V 128K I-TEMP,PB-FREE, 100-
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148RTE20IV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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4.1
4.1.1
As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions
are accepted at all times in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on
the interrupt control mode set by the INTM0 and INTM1 bits in SYSCR.
Table 4.1
Notes: 1. Traces are enabled only in interrupt control modes 2 and 3. (They cannot be used in
Priority
High
Low
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
3. Trap instruction exception handling requests are accepted at all times in the program
Exception Handling Types and Priority
Overview
this LSI.) Trace exception handling is not executed after execution of an RTE
instruction.
instruction execution, or on completion of reset exception handling.
execution state.
Exception Type
Reset
Trace *
Interrupt
Direct transition
Trap instruction (TRAPA) *
Exception Types and Priority
1
Section 4 Exception Handling
3
Start of Exception Handling
Starts immediately after a low-to-high transition at the
RES pin, or when the watchdog timer overflows.
Starts when execution of the current instruction or
exception handling ends, if the trace (T) bit is set to 1.
exception handling ends, if an interrupt request has been
issued. *
Started by a direct transition resulting from execution of a
SLEEP instruction.
Started by execution of a trap instruction (TRAPA).
Starts when execution of the current instruction or
2
Rev. 4.00 Sep 27, 2006 page 103 of 1130
Section 4 Exception Handling
REJ09B0327-0400
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