DF2148RTE20IV Renesas Electronics America, DF2148RTE20IV Datasheet - Page 710

• Manufacturer Part Number: DF2148RTE20IV
• Description: MCU 5V 128K I-TEMP,PB-FREE, 100-
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148RTE20IV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 22 ROM
Rev. 4.00 Sep 27, 2006 page 664 of 1130
REJ09B0327-0400
Increment address
NG
(Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Write 32-byte data in RAM reprogram data
Store 32-byte program data in program
Transfer reprogram data to reprogram
H'FF dummy write to verify address
data area and reprogram data area
area consecutively to flash memory
Figure 22.12 Program/Program-Verify Flowchart
Reprogram data computation
Clear SWE bit in FLMCR1
Clear PSU bit in FLMCR2
Set SWE bit in FLMCR1
Clear PV bit in FLMCR1
Set PSU bit in FLMCR2
Clear P bit in FLMCR1
Set PV bit in FLMCR1
Set P bit in FLMCR1
End of programming
Read verify data
data verification?
Program data =
End of 32-byte
Disable WDT
Enable WDT
Wait ( ) s
Wait ( ) s
Wait ( ) s
Wait (x) s
Wait (y) s
Wait (z) s
Wait ( ) s
Wait ( ) s
verify data?
OK
data area
m = 0?
m = 0
n = 1
Start
OK
OK
NG
NG
*5
*4
*1
*5
Start of programming
*5
End of programming
*5
*5
*5
*5
*2
*3
*4
*5
m = 1
Notes: 1. Data transfer is performed by byte transfer. The lower
Clear SWE bit in FLMCR1
Programming failure
Program
Data
0
0
1
1
2. Verify data is read in 16-bit (word) units.
3. If a bit for which programming has been completed in the 32-byte
4. An area for storing program data (32 bytes) and reprogram data
5. See section 26.2.6, Flash Memory Characteristics, for the values
8 bits of the first address written to must be H'00, H'20, H'40,
H'60, H'80, H'A0, H'C0, or H'E0. A 32-byte data transfer
must be performed even if writing fewer than 32 bytes;
in this case, H'FF data must be written to the extra addresses.
programming loop fails the following verify phase, additional
programming is performed for that bit.
(32 bytes) must be provided in RAM. The contents of the latter
are rewritten as programming progresses.
of x, y, z, , , , , , and N.
n
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
N?
0
1
0
1
Verify
Data
OK
*5
Reprogram
Data
1
0
1
1
NG
n
n + 1
Comments
Reprogramming is not
performed if program data
and verify data match
Programming incomplete;
reprogram
—
Still in erased state;
no action
Reprogram data storage
Program data storage
area (32 bytes)
area (32 bytes)
RAM