DF2376VFQ33V Renesas Electronics America, DF2376VFQ33V Datasheet - Page 914
![IC H8S/2376 MCU FLASH 144LQFP](/photos/28/61/286116/144-lqfp__plqp0144kc-a_sml.jpg)
DF2376VFQ33V
Manufacturer Part Number
DF2376VFQ33V
Description
IC H8S/2376 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2376VFQ33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
30K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Quantity
Price
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Part Number:
DF2376VFQ33V
Manufacturer:
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Quantity:
10 000
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Section 20 Flash Memory (0.35-μm F-ZTAT Version)
20.6
In an on-board programming mode, programming, erasing, and verification for the on-chip flash
memory can be performed. There are two on-board programming modes: boot mode and user
program mode. Table 20.4 shows how to select boot mode. User program mode can be selected by
setting the control bits by software. For a diagram that shows mode transitions of flash memory,
see figure 20.2.
Table 20.4 Setting On-Board Programming Mode
Boot mode
20.6.1
When this LSI enters boot mode, the embedded boot program is started. The boot program
transfers the programming control program from the externally connected host to the on-chip
RAM via the SCI_1. When the flash memory is all erased, the programming control program is
executed.
Table 20.5 shows the boot mode operations between reset end and branching to the programming
control program.
1. When the boot program is initiated, the SCI_1 should be set to asynchronous mode, the chip
2. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the end of
Rev.7.00 Mar. 18, 2009 page 846 of 1136
REJ09B0109-0700
measures the low-level period of asynchronous SCI communication data (H'00) transmitted
continuously from the host. The chip then calculates the bit rate of transmission from the host,
and adjusts the SCI_1 bit rate to match that of the host. The transfer format is 8-bit data, 1 stop
bit, and no parity. The reset should end with the RxD pin high. The RxD and TxD pins should
be pulled up on the board if necessary. After the reset ends, it takes approximately 100 states
before the chip is ready to measure the low-level period.
bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has
been received normally, and transmit one H'55 byte to the chip. If reception could not be
performed normally, initiate boot mode again by a reset. Depending on the host’s transfer bit
rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates
of the host and the chip. To operate the SCI properly, set the host’s transfer bit rate and system
clock frequency of this LSI within the ranges listed in table 20.6.
On-Board Programming Modes
Boot Mode
Mode Setting
Single-chip activation expanded
mode with on-chip ROM enabled
MD2
0
MD1
1
MD0
1
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