DF2376VFQ33V Renesas Electronics America, DF2376VFQ33V Datasheet - Page 287
![IC H8S/2376 MCU FLASH 144LQFP](/photos/28/61/286116/144-lqfp__plqp0144kc-a_sml.jpg)
DF2376VFQ33V
Manufacturer Part Number
DF2376VFQ33V
Description
IC H8S/2376 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2376VFQ33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
30K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2376VFQ33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Table 6.9
Pin
CS2
CS3
CS4
CS5
(OE)
UCAS
LCAS
A15 to A0
D15 to D0
DCTL
Synchronous DRAM Interface Pins
With
Synchronous
DRAM Setting
RAS
CAS
WE
SDRAMφ
(CKE)
DQMU
DQML
A15 to A0
D15 to D0
DCTL
Name
Row address strobe
Column address strobe
Write enable
Clock
Clock enable
Upper data mask enable Output
Lower data mask enable Output
Address pins
Data pins
Device control pin
Rev.7.00 Mar. 18, 2009 page 219 of 1136
I/O
Output
Output
Output
Output
Output
Output
I/O
Input
Section 6 Bus Controller (BSC)
Function
Row address strobe when
areas 2 to 5 are designated as
continuous synchronous
DRAM space
Column address strobe when
areas 2 to 5 are designated as
continuous synchronous
DRAM space
Write enable strobe when
areas 2 to 5 are designated as
continuous synchronous
DRAM space
Clock only for synchronous
DRAM
Clock enable signal when
areas 2 to 5 are designated as
continuous synchronous
DRAM space
Upper data mask enable for
16-bit continuous synchronous
DRAM space access/data
mask enable for 8-bit
continuous synchronous
DRAM space access
Lower data mask enable
signal for 16-bit continuous
synchronous DRAM space
access
Row address/column address
multiplexed output pins
Data input/output pins
Output enable pin for SDRAMφ
REJ09B0109-0700
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