DF2376VFQ33V Renesas Electronics America, DF2376VFQ33V Datasheet - Page 826
![IC H8S/2376 MCU FLASH 144LQFP](/photos/28/61/286116/144-lqfp__plqp0144kc-a_sml.jpg)
DF2376VFQ33V
Manufacturer Part Number
DF2376VFQ33V
Description
IC H8S/2376 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2376VFQ33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
30K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2376VFQ33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 15 Serial Communication Interface (SCI, IrDA)
When turning on the power or switching between Smart Card interface mode and software standby
mode, the following procedures should be followed in order to maintain the clock duty cycle.
Powering On: To secure the clock duty cycle from power-on, the following switching procedure
should be followed.
1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor
2. Fix the SCK pin to the specified output level with the CKE1 bit in SCR.
3. Set SMR and SCMR, and switch to smart card mode operation.
4. Set the CKE0 bit in SCR to 1 to start clock output.
When Changing from Smart Card Interface Mode to Software Standby Mode:
1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to
2. Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive
3. Write 0 to the CKE0 bit in SCR to halt the clock.
4. Wait for one serial clock period.
5. Make the transition to the software standby state.
When Returning to Smart Card Interface Mode from Software Standby Mode:
1. Exit the software standby state.
2. Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the
Rev.7.00 Mar. 18, 2009 page 758 of 1136
REJ09B0109-0700
to fix the potential.
the value for the fixed output state in software standby mode.
operation. At the same time, set the CKE1 bit to the value for the fixed output state in software
standby mode.
During this interval, clock output is fixed at the specified level, with the duty cycle preserved.
normal duty cycle.
[1] [2] [3]
Normal operation
Figure 15.32 Clock Halt and Restart Procedure
[4] [5]
Software
standby
[6]
[7]
Normal operation
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