DF2376VFQ33V Renesas Electronics America, DF2376VFQ33V Datasheet - Page 38
![IC H8S/2376 MCU FLASH 144LQFP](/photos/28/61/286116/144-lqfp__plqp0144kc-a_sml.jpg)
DF2376VFQ33V
Manufacturer Part Number
DF2376VFQ33V
Description
IC H8S/2376 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2376VFQ33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
30K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2376VFQ33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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15.5 Multiprocessor Communication Function.......................................................................... 734
15.6 Operation in Clocked Synchronous Mode ......................................................................... 740
15.7 Operation in Smart Card Interface Mode........................................................................... 748
15.8 IrDA Operation .................................................................................................................. 759
15.9 Interrupt Sources ................................................................................................................ 762
15.10 Usage Notes ....................................................................................................................... 765
Section 16 I
16.1 Features .............................................................................................................................. 771
16.2 Input/Output Pins ............................................................................................................... 773
16.3 Register Descriptions ......................................................................................................... 774
Rev.7.00 Mar. 18, 2009 page xxxvi of lxvi
REJ09B0109-0700
15.4.6 Serial Data Reception (Asynchronous Mode)....................................................... 730
15.5.1 Multiprocessor Serial Data Transmission ............................................................. 735
15.5.2 Multiprocessor Serial Data Reception .................................................................. 737
15.6.1 Clock..................................................................................................................... 740
15.6.2 SCI Initialization (Clocked Synchronous Mode) .................................................. 741
15.6.3 Serial Data Transmission (Clocked Synchronous Mode) ..................................... 741
15.6.4 Serial Data Reception (Clocked Synchronous Mode)........................................... 744
15.6.5 Simultaneous Serial Data Transmission and Reception
15.7.1 Pin Connection Example....................................................................................... 748
15.7.2 Data Format (Except for Block Transfer Mode) ................................................... 749
15.7.3 Block Transfer Mode ............................................................................................ 750
15.7.4 Receive Data Sampling Timing and Reception Margin........................................ 750
15.7.5 Initialization .......................................................................................................... 752
15.7.6 Data Transmission (Except for Block Transfer Mode) ......................................... 753
15.7.7 Serial Data Reception (Except for Block Transfer Mode) .................................... 755
15.7.8 Clock Output Control............................................................................................ 757
15.9.1 Interrupts in Normal Serial Communication Interface Mode................................ 762
15.9.2 Interrupts in Smart Card Interface Mode .............................................................. 764
15.10.1 Module Stop Mode Setting ................................................................................... 765
15.10.2 Break Detection and Processing ........................................................................... 765
15.10.3 Mark State and Break Sending.............................................................................. 765
15.10.4 Receive Error Flags and Transmit Operations
15.10.5 Relation between Writes to TDR and the TDRE Flag .......................................... 766
15.10.6 Restrictions on Use of DMAC or DTC................................................................. 766
15.10.7 Operation in Case of Mode Transition.................................................................. 767
16.3.1 I
16.3.2 I
16.3.3 I
(Clocked Synchronous Mode) .............................................................................. 746
(Clocked Synchronous Mode Only)...................................................................... 766
2
2
2
2
C Bus Control Register A (ICCRA) ................................................................... 775
C Bus Control Register B (ICCRB) ................................................................... 777
C Bus Mode Register (ICMR)............................................................................ 778
C Bus Interface 2 (IIC2) (Option)................................................. 771
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