DF2376VFQ33V Renesas Electronics America, DF2376VFQ33V Datasheet - Page 1006
![IC H8S/2376 MCU FLASH 144LQFP](/photos/28/61/286116/144-lqfp__plqp0144kc-a_sml.jpg)
DF2376VFQ33V
Manufacturer Part Number
DF2376VFQ33V
Description
IC H8S/2376 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2376VFQ33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
30K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2376VFQ33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 21 Flash Memory (0.18-μm F-ZTAT Version)
4. Bit rate
To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register (SMR),
and the value(N) in the bit rate register (BRR), which are found from the peripheral operating
clock frequency (φ) and bit rate (B), are used to calculate the error rate to ensure that it is less than
4%. If the error is more than 4%, a bit rate error is generated. The error is calculated using the
following expression:
When the new bit rate is selectable, the rate will be set in the register after sending ACK in
response. The host will send an ACK with the new bit rate for confirmation and the boot program
will response with that rate.
Confirmation
• Confirmation, H'06, (one byte): Confirmation of a new bit rate
Response
• Response, H'06, (one byte): Response to confirmation of a new bit rate
The sequence of new bit-rate selection is shown in figure 21.20.
Rev.7.00 Mar. 18, 2009 page 938 of 1136
REJ09B0109-0700
Waiting for one-bit period
Setting a new bit rate
at the specified bit rate
Error (%) = {[
H'06
Host
H'06
(N + 1) × B × 64 × 2
Figure 21.20 New Bit-Rate Selection Sequence
φ × 10
H'06 (ACK) with the new bit rate
H'06 (ACK) with the new bit rate
6
Setting a new bit rate
(2×n − 1)
H'06 (ACK)
] − 1} × 100
Setting a new bit rate
Boot program
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