DF2376VFQ33V Renesas Electronics America, DF2376VFQ33V Datasheet - Page 449
![IC H8S/2376 MCU FLASH 144LQFP](/photos/28/61/286116/144-lqfp__plqp0144kc-a_sml.jpg)
DF2376VFQ33V
Manufacturer Part Number
DF2376VFQ33V
Description
IC H8S/2376 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2376VFQ33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
30K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2376VFQ33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another
bus master during burst transfer. If there is no bus request, burst transfer is executed even if the
BGUP bit is set to 1.
Figure 8.6 shows examples of the timing in burst mode.
8.4.5
There are two transfer modes: normal transfer mode and block transfer mode. When the activation
source is an external request, either normal transfer mode or block transfer mode can be selected.
When the activation source is an auto request, normal transfer mode is used.
Normal Transfer Mode: In normal transfer mode, transfer of one transfer unit is processed in
response to one transfer request. EDTCR functions as a 24-bit transfer counter.
The ETEND signal is output only for the last DMA transfer. The EDRAK signal is output each
time a transfer request is accepted and transfer processing is started.
Figure 8.7 shows examples of DMA transfer timing in normal transfer mode.
Bus cycle
Bus cycle
Transfer conditions:
Transfer conditions:
Auto request mode, BGUP = 0
Auto request mode, BGUP = 1
Transfer Modes
CPU
CPU
Figure 8.6 Examples of Timing in Burst Mode
EXDMAC
CPU
EXDMAC
EXDMAC operates alternately with CPU
CPU
EXDMAC
EXDMAC
CPU cycle not generated
Rev.7.00 Mar. 18, 2009 page 381 of 1136
Section 8 EXDMA Controller (EXDMAC)
EXDMAC
CPU
EXDMAC
CPU
REJ09B0109-0700
CPU
CPU
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