MC9S12DT256MPVE Freescale Semiconductor, MC9S12DT256MPVE Datasheet - Page 574

• Manufacturer Part Number: MC9S12DT256MPVE
• Description: IC MCU 256K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12DT256MPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.25 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12D
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 1
• Operating Supply Voltage: 5 V to 2.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68KIT912DP256
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 12KB
• Cpu Speed: 25MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 15 Background Debug Module (S12XBDMV2)
15.3.2.1
Register Global Address 0x7FFF01
1
2
3
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured, but subject to the following:
574
Special Single-Chip Mode
ENBDM is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but
fully erased (Flash and EEPROM). This is because the ENBDM bit is set by the standard firmware before a BDM command
can be fully transmitted and executed.
CLKSW is read as 1 by a debugging environment in emulation modes when the device is not secured and read as 0 when
secured.
UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased,
else it is 0 and can only be read if not secure (see also bit description).
ENBDM
Field
7
— ENBDM should only be set via a BDM hardware command if the BDM firmware commands
— BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by
— CLKSW can only be written via BDM hardware WRITE_BD commands.
— All other bits, while writable via BDM hardware or standard BDM firmware write commands,
Emulation Modes
All Other Modes
are needed. (This does not apply in special single chip and emulation modes).
the standard BDM firmware lookup table upon exit from BDM active mode.
should only be altered by the BDM hardware or standard firmware lookup table as part of BDM
command execution.
Enable BDM — This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made
active to allow firmware commands to be executed. When disabled, BDM cannot be made active but BDM
hardware commands are still allowed.
0 BDM disabled
1 BDM enabled
Note: ENBDM is set by the firmware out of reset in special single chip mode and by hardware in emulation
BDM Status Register (BDMSTS)
Reset
modes. In special single chip mode with the device secured, this bit will not be set by the firmware until
after the EEPROM and Flash erase verify tests are complete. In emulation modes with the device
secured, the BDM operations are blocked.
W
R
ENBDM
0
1
0
0
7
1
Figure 15-3. BDM Status Register (BDMSTS)
Table 15-2. BDMSTS Field Descriptions
= Unimplemented, Reserved
= Always read zero
BDMACT
MC9S12XDP512 Data Sheet, Rev. 2.21
1
0
0
6
0
0
0
0
5
Description
SDV
0
0
0
4
TRACE
0
0
0
3
= Implemented (do not alter)
CLKSW
1
0
0
2
2
Freescale Semiconductor
UNSEC
0
1
0
0
3
0
0
0
0
0