MC9S12DT256MPVE Freescale Semiconductor, MC9S12DT256MPVE Datasheet - Page 166

• Manufacturer Part Number: MC9S12DT256MPVE
• Description: IC MCU 256K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12DT256MPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.25 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12D
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 1
• Operating Supply Voltage: 5 V to 2.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68KIT912DP256
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 12KB
• Cpu Speed: 25MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
5.3.2.1
Writes to this register will abort current conversion sequence but will not start a new sequence.
Read: Anytime
Write: Anytime
166
WRAP[2:0]
ATDD47H
ATDD47L
Reset
Register
Field
Name
2–0
W
R
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing
multi-channel conversions. The coding is summarized in
ATD Control Register 0 (ATDCTL0)
0
0
7
10-BIT
10-BIT
8-BIT
8-BIT
WRAP2
W
= Unimplemented or Reserved
0
0
0
0
1
1
1
1
BIT 7 MSB
BIT 7
Bit 7
0
0
6
0
0
Figure 5-2. ATD Register Summary (Sheet 5 of 5)
Table 5-2. Multi-Channel Wrap Around Coding
Figure 5-3. ATD Control Register 0 (ATDCTL0)
WRAP1
0
0
1
1
0
0
1
1
= Unimplemented or Reserved
Table 5-1. ATDCTL0 Field Descriptions
BIT 6
BIT 6
MC9S12XDP512 Data Sheet, Rev. 2.21
6
0
0
0
0
5
WRAP0
0
1
0
1
0
1
0
1
BIT 5
BIT 5
5
0
0
Multiple Channel Conversions (MULT = 1)
0
0
4
Wrap Around to AN0 after Converting
Description
BIT 4
BIT 4
4
0
0
Table
0
0
3
Reserved
5-2.
BIT 3
BIT 3
AN1
AN2
AN3
AN4
AN5
AN6
AN7
3
0
0
WRAP2
1
2
BIT 2
BIT 2
2
0
0
WRAP1
Freescale Semiconductor
BIT 9 MSB
1
1
BIT 1
BIT 1
1
0
WRAP0
BIT 8
BIT 0
BIT 0
Bit 0
1
0
0