MC9S12DT256MPVE Freescale Semiconductor, MC9S12DT256MPVE Datasheet - Page 483
![IC MCU 256K FLASH 25MHZ 112-LQFP](/photos/37/62/376255/lqfp-112_sml.jpg)
MC9S12DT256MPVE
Manufacturer Part Number
MC9S12DT256MPVE
Description
IC MCU 256K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S912XDG128F2MAL.pdf
(1348 pages)
Specifications of MC9S12DT256MPVE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
PWM, WDT
Number Of I /o
91
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.25 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Processor Series
S12D
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
91
Number Of Timers
1
Operating Supply Voltage
5 V to 2.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68KIT912DP256
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (8-ch x 10-bit)
No. Of I/o's
91
Eeprom Memory Size
4KB
Ram Memory Size
12KB
Cpu Speed
25MHz
No. Of Timers
1
No. Of Pwm Channels
8
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12DT256MPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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11.3.2.2
Read: Anytime, if AMAP = 0.
Write: Anytime, if AMAP = 0.
Freescale Semiconductor
SCISWAI
LOOPS
Reset
WAKE
RSRC
Field
M
7
6
5
4
3
W
R
LOOPS
Loop Select Bit — LOOPS enables loop operation. In loop operation, the RXD pin is disconnected from the SCI
and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must
be enabled to use the loop function.
0 Normal operation enabled
1 Loop operation enabled
The receiver input is determined by the RSRC bit.
SCI Stop in Wait Mode Bit — SCISWAI disables the SCI in wait mode.
0 SCI enabled in wait mode
1 SCI disabled in wait mode
Receiver Source Bit — When LOOPS = 1, the RSRC bit determines the source for the receiver shift register
input. See
0 Receiver input internally connected to transmitter output
1 Receiver input connected externally to transmitter
Data Format Mode Bit — MODE determines whether data characters are eight or nine bits long.
0 One start bit, eight data bits, one stop bit
1 One start bit, nine data bits, one stop bit
Wakeup Condition Bit — WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the
most significant bit position of a received data character or an idle condition on the RXD pin.
0 Idle line wakeup
1 Address mark wakeup
SCI Control Register 1 (SCICR1)
0
7
This register is only visible in the memory map if AMAP = 0 (reset
condition).
Table
SCISWAI
0
6
11-4.
TNP[1:0]
Figure 11-5. SCI Control Register 1 (SCICR1)
11
10
01
00
Table 11-2. IRSCI Transmit Pulse Width
Table 11-3. SCICR1 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
RSRC
0
5
NOTE
M
0
4
Narrow Pulse Width
Description
WAKE
1/32
1/16
3/16
1/4
Chapter 11 Serial Communication Interface (S12SCIV5)
0
3
ILT
0
2
PE
0
1
PT
0
0
483
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