MC9S12DT256MPVE Freescale Semiconductor, MC9S12DT256MPVE Datasheet - Page 1021

• Manufacturer Part Number: MC9S12DT256MPVE
• Description: IC MCU 256K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12DT256MPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.25 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12D
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 1
• Operating Supply Voltage: 5 V to 2.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68KIT912DP256
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 12KB
• Cpu Speed: 25MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PERJ[7:6]
PERJ[1:0]
PPSJ[7:6]
PPSJ[1:0]
Reset
Reset
Field
24.0.5.55 Port J Polarity Select Register (PPSJ)
Read: Anytime.
Write: Anytime.
This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as
selecting a pull-up or pull-down device if enabled.
Field
24.0.5.56 Port J Interrupt Enable Register (PIEJ)
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated
with Port J.
7–0
7–0
W
W
R
R
PPSJ7
PIEJ7
Pull Device Enable Port J
0 Pull-up or pull-down device is disabled.
1 Either a pull-up or pull-down device is enabled.
Polarity Select Port J
0 Falling edge on the associated port J pin sets the associated flag bit in the PIFJ register.
1 Rising edge on the associated port J pin sets the associated flag bit in the PIFJ register.
7
0
7
0
A pull-up device is connected to the associated port J pin, if enabled by the associated bit in register PERJ
and if the port is used as general purpose input or as IIC port.
A pull-down device is connected to the associated port J pin, if enabled by the associated bit in register PERJ
and if the port is used as input.
= Unimplemented or Reserved
= Unimplemented or Reserved
PPSJ6
PIEJ6
0
0
6
6
Figure 24-58. Port J Interrupt Enable Register (PIEJ)
Figure 24-57. Port J Polarity Select Register (PPSJ)
Table 24-50. PERJ Field Descriptions
Table 24-51. PPSJ Field Descriptions
5
0
0
5
0
0
0
0
0
0
4
4
Description
Description
3
0
0
3
0
0
0
0
0
0
2
2
PPSJ1
PIEJ1
1
0
1
0
PPSJ0
PIEJ0
0
0
0
0