MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 33

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the corresponding bit in port A an output; clearing a bit in DDRA makes the corresponding bit in port A an
input. The default reset state of DDRA is all 0s.
When the PUPA bit in the PUCR register is set, all port A input pins are pulled up internally by an active
pullup device. This bit has no effect if the port is being used in expanded modes as the pullups are
inactive.
Setting the RDPA bit in the reduced drive register (RDRIV) causes all port A outputs to have reduced drive
levels. RDRIV can be written once after reset and is not in the address map in peripheral mode. Refer to
Chapter 6 Bus Control and Input/Output
1.6.4.2 Port B
Port B pins are used for address and data in expanded modes. The port data register is not in the address
map during expanded and peripheral mode operation. When it is in the map, port B can be read or written
at anytime.
The port B data direction register (DDRB) determines whether each port B pin is an input or output. DDRB
is not in the address map during expanded and peripheral mode operation. Setting a bit in DDRB makes
the corresponding bit in port B an output; clearing a bit in DDRB makes the corresponding bit in port B an
input. The default reset state of DDRB is all 0s.
When the PUPB bit in the PUCR register is set, all port B input pins are pulled up internally by an active
pullup device. This bit has no effect if the port is being used in expanded modes because the pullups are
inactive.
Setting the RDPB bit in register RDRIV causes all port B outputs to have reduced drive levels. RDRIV can
be written once after reset. RDRIV is not in the address map in peripheral mode. Refer to
Control and Input/Output
1.6.4.3 Port E
Port E pins operate differently from port A and B pins. Port E pins are used for bus control signals and
interrupt service request signals. When a pin is not used for one of these specific functions, it can be used
as general-purpose I/O. However, two of the pins, PE1 and PE0, can be used only for input, and the states
of these pins can be read in the port data register even when they are used for IRQ and XIRQ.
The PEAR register determines pin function, and the data direction register (DDRE) determines whether
each pin is an input or output when it is used for general-purpose I/O. PEAR settings override DDRE
settings. Because PE1 and PE0 are input-only pins, only DDRE7–DDRE2 have effect. Setting a bit in the
DDRE register makes the corresponding bit in port E an output; clearing a bit in the DDRE register makes
the corresponding bit in port E an input. The default reset state of DDRE is all 0s.
When the PUPE bit in the PUCR register is set, PE7, PE3, PE2, and PE0 are pulled up. PE7, PE3, PE2,
and PE0 are active pulled-up devices, while PE1 is always pulled up by means of an internal resistor.
Port E and DDRE are not in the map in peripheral mode or in expanded modes when the EME bit in the
MODE register is set.
Setting the RDPE bit in register RDRIV causes all port E outputs to have reduced drive level. RDRIV can
be written once after reset. RDRIV is not in the address map in peripheral mode. Refer to
Control and Input/Output
Freescale Semiconductor
(I/O).
(I/O).
M68HC12B Family Data Sheet, Rev. 9.1
(I/O).
Pinout and Signal Descriptions
Chapter 6 Bus
Chapter 6 Bus
33