MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 148

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Standard Timer (TIM)
12.3.8 Timer Interrupt Flag Registers
Read: Anytime
Write: Used in the clearing mechanism; set bits cause corresponding bits to
TFLG1 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write a 1 to
the bit. Writing a logic 0 does not affect current status of the bit.
When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare
channel ($90–$9F) causes the corresponding channel flag CnF to be cleared.
C7F–C0F — Input Capture/Output Compare Channel n Flag
Read: Anytime
Write: Used in the clearing mechanism; set bits cause corresponding bits to
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, set the bit to 1.
Any access to TCNT clears TFLG2 register, if the TFFCA bit in TSCR register is set.
TOF — Timer Overflow Flag
148
Set when 16-bit free-running timer overflows from $FFFF to $0000. This bit is cleared automatically by
a write to the TFLG2 register with bit 7 set. For additional information, see the TCRE control bit
explanation found in
be cleared
be cleared
Address: $008E
Address: $008F
Reset:
Reset:
Read:
Read:
Write:
Write:
Bit 7
C7F
Bit 7
TOF
12.3.7 Timer Interrupt Mask
0
0
Figure 12-14. Timer Interrupt Flag 1 (TFLG1)
Figure 12-15. Timer Interrupt Flag 2 (TFLG2)
C6F
6
0
6
0
0
M68HC12B Family Data Sheet, Rev. 9.1
C5F
5
0
5
0
0
C4F
4
0
4
0
0
Registers.
C3F
3
0
3
0
0
C2F
2
0
2
0
0
C1F
1
0
1
0
0
Freescale Semiconductor
Bit 0
Bit 0
C0F
0
0
0