MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 170

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Capture Timer (ECT) Module
Read: Anytime
Write: Anytime
EDGnB and EDGnA — Input Capture Edge Control Bits
170
To operate the 16-bit pulse accumulators A and B (PACA and PACB) independently of input capture
or output compare 7 and 0, respectively, the user must set the corresponding bits IOSn = 1, OMn = 0,
and OLn = 0. OC7M7 or OC7M0 in the OC7M register must also be cleared.
These eight pairs of control bits configure the input capture edge detector circuits. See
Address: $008A
Address: $008B
Reset:
Reset:
Read:
Read:
Write:
Write:
EDG7B
EDG3B
OMn
Bit 7
Bit 7
EDGnB
0
0
0
0
1
1
Table 13-2. Edge Detector Circuit Configuration
Figure 13-14. Timer Control Register 3 (TCTL3)
Figure 13-15. Timer Control Register 4 (TCTL4)
0
0
1
1
Table 13-1. Compare Result Output Action
OLn
EDG7A
EDG3A
0
1
0
1
6
0
6
0
M68HC12B Family Data Sheet, Rev. 9.1
EDGnA
Timer disconnected from output pin logic
Toggle OCn output line
Clear OCn output line to 0
Set OCn output line to 1
0
1
0
1
EDG6B
EDG2B
5
0
5
0
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge (rising or falling)
EDG6A
EDG2A
4
0
4
0
Action
Configuration
EDG5B
EDG1B
3
0
3
0
EDG5A
EDG1A
2
0
2
0
EDG4B
EDG0B
1
0
1
0
Freescale Semiconductor
EDG4A
EDG0A
Bit 0
Bit 0
0
0
Table
13-2.