MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 273

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AC7–AC0 — Acceptance Code Bits
16.12.13 msCAN12 Identifier Mask Registers
The identifier mask register specifies which of the corresponding bits in the identifier acceptance register
are relevant for acceptance filtering. To receive standard identifiers in 32-bit filter mode, the last three bits
(AM2–AM0) in the mask registers CIDMR1 and CIDMR5 must be programmed to don’t care. To receive
standard identifiers in 16 bit filter mode the last three bits (AM2–AM0) in the mask registers CIDMR1,
CIDMR3, CIDMR5, and CIDMR7 must be programmed to don’t care.
Freescale Semiconductor
AC7–AC0 comprise a user-defined sequence of bits with which the corresponding bits of the related
identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is
then masked with the corresponding identifier mask register.
Address: $0118
Address: $0119
Address: $011A
Address: $011B
The CIDAR0-CIDAR7 registers can be written only if the SFTRES bit in
CMCR0 is set.
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Figure 16-28. Second Bank msCAN12 Identifier Acceptance
Bit 7
AC7
Bit 7
AC7
Bit 7
AC7
Bit 7
AC7
AC6
AC6
AC6
AC6
6
6
6
6
M68HC12B Family Data Sheet, Rev. 9.1
Registers (CIDAR4–CIDAR7)
AC5
AC5
AC5
AC5
5
5
5
5
NOTE
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
AC4
AC4
AC4
AC4
4
4
4
4
AC3
AC3
AC3
AC3
3
3
3
3
Programmer’s Model of Control Registers
AC2
AC2
AC2
AC2
2
2
2
2
AC1
AC1
AC1
AC1
1
1
1
1
Bit 0
AC0
Bit 0
AC0
Bit 0
AC0
Bit 0
AC0
273