MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 216

IC MCU 32K FLASH 8MHZ 80-QFP

MCHC912B32CFUE8

Manufacturer Part Number
MCHC912B32CFUE8
Description
IC MCU 32K FLASH 8MHZ 80-QFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MCHC912B32CFUE8

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
63
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
768 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Cpu Family
HC12
Device Core Size
16b
Frequency (max)
8MHz
Interface Type
SCI/SPI
Total Internal Ram Size
1KB
# I/os (max)
63
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Package
80PQFP
Family Name
HC12
Maximum Speed
8 MHz
Operating Supply Voltage
5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
63
Processor Series
HC912B
Core
HC12
Data Ram Size
1 KB
Maximum Clock Frequency
8 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912B32E
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCHC912B32CFUE8
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MCHC912B32CFUE8
Quantity:
300
Byte Data Link Communications (BDLC)
To disengage a BDLC node from receiving J1850 traffic:
The BDLC can then be put into wait mode or stop mode and does not wake up with J1850 traffic.
Depending upon which low-power mode instruction the CPU executes and which mode the BDLC enters,
the message which wakes up the BDLC (and the CPU) may not be received correctly. Three possibilities
are described here. These descriptions apply regardless of whether the BDLC is in normal or 4X mode
when the STOP or WAIT instruction is executed.
15.5.1 BDLC Wait and CPU Wait Mode
This power-saving mode is entered automatically from run mode when the WCM bit in BCR1 register is
cleared followed by a CPU WAIT instruction. In BDLC wait mode, the BDLC cannot drive data. A
subsequent J1850 network rising edge wakes up the BDLC.
In this mode, the BDLC internal clocks continue to run as do the MCU clocks. The first passive-to-active
transition on the J1850 network generates a CPU interrupt request by the BDLC which wakes up the
BDLC and CPU. The BDLC correctly receives the entire message which generated the CPU interrupt
request.
15.5.2 BDLC Stop and CPU Wait Mode
This power-conserving mode is entered automatically from run mode when the WCM bit in the BCR1
register is set followed by a CPU WAIT instruction. This is the lowest-power mode that the BDLC can
enter.
In this mode:
The first passive-to-active transition on the J1850 network generates a non-maskable ($20) CPU interrupt
request by the BDLC, allowing the CPU to restart the BDLC internal clocks.
To correctly receive future J1850 wakeup traffic, users must read an EOF (end of frame) in the BSVR
prior to placing the BDLC into stop mode (WCM = 1). Then, the new message which wakes up the BDLC
from the BDLC stop mode and the CPU from the CPU wait mode, is received correctly.
216
Verify all BSVR flags are clear.
Do not load the BDR.
Set the ALOOP bit (after placing the analog transceiver into loopback mode) or DLOOP bit in
BCR2.
The BDLC internal clocks are stopped.
The CPU internal clocks continue to run.
The BDLC awaits J1850 network activity.
Ensure that all transmissions are complete or aborted prior to putting the
BDLC into wait mode (WCM = 0 in BCR1).
Ensure that all transmissions are complete or aborted prior to putting the
BDLC into stop mode (WCM = 1 in BCR1).
M68HC12B Family Data Sheet, Rev. 9.1
NOTE
NOTE
Freescale Semiconductor

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