MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 101

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

GADR — Gate/Drain Stress Test Select Bit
HVT — Stress Test High Voltage Status Bit
FENLV — Enable Low Voltage Bit
FDISVFP — Disable Status V
VTCK — V
STRE — Spare Test Row Enable Bit
MWPR — Multiple Word Programming Bit
Freescale Semiconductor
When the V
the LAT bit; the user cannot erase or program the FLASH module. The FDISVFP control bit enables
writing to the LAT bit regardless of the voltage on the V
When VTCK is set, the FLASH EEPROM module uses the V
the sense amp timeout path is disabled. This allows for indirect measurements of the bit cells’ program
and erase threshold. If V
If V
Control gate voltage = V
The spare test row consists of one FLASH EEPROM array row. The spare test row is reserved and
contains production test information which must be maintained through several erase cycles. When
STRE is set, the decoding for the spare test row overrides the address lines which normally select the
other rows in the array.
Used primarily for testing, if MPWR = 1, the two least significant address lines, ADDR1 and ADDR0,
will be ignored when programming a FLASH EEPROM location. The word location addressed if
ADDR1 and ADDR0 = 00, along with the word location addressed if ADDR1 and ADDR0 = 10, will both
be programmed with the same word data from the programming latches. This bit should not be
changed during programming.
0 = Selects the drain stress circuitry
1 = Selects the gate stress circuitry
0 = High voltage not present during stress test
1 = High voltage present during stress test
0 = Disables low voltage transistor in current reference circuit
1 = Enables low voltage transistor in current reference circuit
0 = Enable the automatic lock mechanism if V
1 = Disable the automatic lock mechanism if V
0 = V
1 = V
0 = LIB accesses are to the FLASH EEPROM array.
1 = Spare test row in array enabled if SMOD is active
0 = Multiple word programming disabled
1 = Program 32 bits of data
FP
> V
T
T
T
ZBRK
Check Test Enable Bit
test disable
test enable
FP
, the control gate will be regulated by this equation:
pin is below normal programming voltage, the FLASH module will not allow writing to
ZBRK
FP
< V
FP
+ 0.44 × (V
Voltage Lock Bit
ZBRK
M68HC12B Family Data Sheet, Rev. 9.1
(breakdown voltage), the control gate will equal the V
FP
− V
ZBRK
FP
FP
is low.
)
is low.
FP
pin.
FP
pin to control the control gate voltage;
FLASH EEPROM Registers
FP
voltage.
101