MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 90

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bus Control and Input/Output (I/O)
CGMTE — CGM Test Output Enable
PIPOE — Pipe Signal Output Enable Bit
NECLK — No External E Clock Bit
LSTRE — Low Strobe (LSTRB) Enable Bit
RDWE — Read/Write Enable Bit
90
Normal: Write once
Special: Write anytime except the first time.
This bit is read at anytime.
Normal: Write once
Special: Write anytime except the first time.
This bit has no effect in single chip modes.
In expanded modes, writes to this bit have no effect. E clock is required for demultiplexing the external
address; NECLK remains 0 in expanded modes. NECLK can be written once in normal single-chip
mode and can be written anytime in special single-chip mode.
Normal: Write once
Special: Write anytime except the first time
This bit has no effect in single-chip modes or normal expanded narrow mode.
LSTRB is used during external writes. After reset in normal expanded mode, LSTRB is disabled. If
needed, it should be enabled before external writes. External reads do not normally need LSTRB
because all 16 data bits can be driven even if the MCU only needs eight bits of data.
TAGLO is a shared function of the PE3/LSTRB pin. In special expanded modes with LSTRE set and
the BDM instruction tagging on, a 0 at the falling edge of E tags the instruction word low byte being
read into the instruction queue.
Normal: Write once
Special: Write anytime except the first time
This bit has no effect in single-chip modes.
R/W is used for external writes. After reset in normal expanded mode, it is disabled. If needed, it should
be enabled before any external writes.
1 = PE6 is a test signal output from the CGM module (no effect in single chip or normal expanded
0 = PE6 is a general-purpose I/O or pipe output.
1 = PE6–PE5 are outputs and indicate state of instruction queue.
0 = PE6–PE5 are general-purpose I/O.
1 = PE4 is a general-purpose I/O pin.
0 = PE4 is the external E clock pin subject to this limitation: In single-chip modes, PE4 is
1 = PE3 is configured as the LSTRB bus-control output.
0 = PE3 is a general-purpose I/O pin.
1 = PE2 configured as R/W pin
0 = PE2 configured as general-purpose I/O pin
modes). PIPOE = 1 overrides this function and forces PE6 to be a pipe status output signal.
general-purpose I/O unless NECLK = 0 and either IVIS = 1 or ESTR = 0. A 16-bit write to
PEAR:MODE can configure all three bits in one operation.
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor