MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 182

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Capture Timer (ECT) Module
13.4.18 Input Control Overwrite Register
Read: Anytime
Write: Anytime
An IC register is empty when it has been read or latched into the holding register. A holding register is
empty when it has been read.
NOVWx — No Input Capture Overwrite Bits
13.4.19 Input Control System Control Register
Read: Anytime
Write: May be written once (SMODN = 1). Writes are always permitted when
SHxy — Share Input Action of Input Capture Channels x and y Bits
TFMOD — Timer Flag-Setting Mode Bit
182
Use of the TFMOD bit in the ICSYS register ($AB) in conjunction with the use of the ICOVW register
($AA) allows a timer interrupt to be generated after capturing two values in the capture and holding
registers instead of generating an interrupt for every capture.
0 = The contents of the related capture register or holding register can be overwritten when a new
1 = The related capture register or holding register cannot be written by an event unless they are
0 = Normal operation
1 = The channel input x causes the same action on the channel y. The port pin x and the
SMODN = 0.
input capture or latch occurs.
empty (see
is read or latched in the holding register.
corresponding edge detector is used to be active on the channel y.
Address: $00AA
Address: $00AB
Reset:
Reset:
Read:
Read:
Write:
Write:
Figure 13-40. Input Control System Control Register (ICSYS)
13.3.1 IC
Figure 13-39. Input Control Overwrite Register (ICOVW)
NOVW7
SH37
Bit 7
Bit 7
0
0
NOVW6
Channels). This will prevent the captured value to be overwritten until it
SH26
6
0
6
0
M68HC12B Family Data Sheet, Rev. 9.1
NOVW5
SH15
5
0
5
0
NOVW4
SH04
4
0
4
0
NOVW3
TFMOD
3
0
3
0
NOVW2
PACMX
2
0
2
0
NOVW1
BUFEN
1
0
1
0
Freescale Semiconductor
NOVW0
LATQ
Bit 0
Bit 0
0
0