MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 178

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Capture Timer (ECT) Module
13.4.13 Pulse Accumulators Count Registers
Read: Anytime
Write: Anytime
The two 8-bit pulse accumulators, PAC3 and PAC2, are cascaded to form the PACA 16-bit pulse
accumulator. When PACA in enabled (PAEN = 1 in PACTL, $A0) the PACN3 and PACN2 registers’
contents are, respectively, the high and low bytes of the PACA.
When PACN3 overflows from $FF to $00, the interrupt flag PAOVF in PAFLG ($A1) is set. Full count
register access should take place in one clock cycle. A separate read/write for high byte and low byte will
give a different result than accessing them as a word.
Read: Anytime
Write: Anytime
178
Address: $00A2
Address: $00A3
Address: $00A4
Address: $00A5
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Figure 13-31. Pulse Accumulator Count Register 3 (PACN3)
Figure 13-32. Pulse Accumulator Count Register 2 (PACN2)
Figure 13-33. Pulse Accumulator Count Register 1 (PACN1)
Figure 13-34. Pulse Accumulator Count Register 0 (PACN0)
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
0
0
0
0
Bit 6
Bit 6
Bit 6
Bit 6
6
0
6
0
6
0
6
0
M68HC12B Family Data Sheet, Rev. 9.1
Bit 5
Bit 5
Bit 5
Bit 5
5
0
5
0
5
0
5
0
Bit 4
Bit 4
Bit 4
Bit 4
4
0
4
0
4
0
4
0
Bit 3
Bit 3
Bit 3
Bit 3
3
0
3
0
3
0
3
0
Bit 2
Bit 2
Bit 2
Bit 2
2
0
2
0
2
0
2
0
Bit 1
Bit 1
Bit 1
Bit 1
1
0
1
0
1
0
1
0
Freescale Semiconductor
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
0
0
0
0