MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 304

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Development Support
18.4.2.5 Breakpoint Data Register High
These bits are compared to the most significant byte of the data bus in full breakpoint mode or the most
significant byte of the address bus in dual address modes. BKE1, BKE0, BKDBE, and BKMBH control
how this byte is used in the breakpoint comparison.
18.4.2.6 Breakpoint Data Register Low Byte
These bits are compared to the least significant byte of the data bus in full breakpoint mode or the least
significant byte of the address bus in dual address modes. BKEN1, BKEN0, BKDBE, BK1ALE, and
BKMBL control how this byte is used in the breakpoint comparison.
18.5 Instruction Tagging
The instruction queue and cycle-by-cycle CPU activity can be reconstructed in real time or from trace
history that was captured by a logic analyzer. However, the reconstructed queue cannot be used to stop
the CPU at a specific instruction, because execution has already begun by the time an operation is visible
outside the MCU. A separate instruction tagging mechanism is provided for this purpose.
Executing the BDM TAGGO command configures two MCU pins for tagging. Tagging information is
latched on the falling edge of ECLK along with program information as it is fetched. Tagging is allowed in
all modes. Tagging is disabled when BDM becomes active and BDM serial commands cannot be
processed while tagging is active.
TAGHI is a shared function of the BKGD pin.
TAGLO is a shared function of the PE3/LSTRB pin, a multiplexed I/O pin. For 1/4 cycle before and after
the rising edge of the E clock, this pin is the LSTRB driven output.
TAGLO and TAGHI inputs are captured at the falling edge of the E clock. A logic 0 on TAGHI and/or
TAGLO marks (tags) the instruction on the high and/or low byte of the program word that was on the data
bus at the same falling edge of the E clock.
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Power on reset:
Power on reset:
After a power-on reset, registers BRKAH, BRKAL, BRKDH, and BRKDL are
cleared but these registers are not affected by normal resets.
Address: $0024
Address: $0025
Read:
Read:
Write:
Write:
Figure 18-14. Breakpoint Data Register High (BRKDH)
Figure 18-15. Breakpoint Data Register Low (BRKDL)
Bit 15
Bit 7
Bit 7
Bit 7
0
0
M68HC12B Family Data Sheet, Rev. 9.1
14
6
0
6
6
0
13
5
0
5
5
0
NOTE
12
4
0
4
4
0
11
3
0
3
3
0
10
2
0
2
2
0
1
9
0
1
1
0
Freescale Semiconductor
Bit 0
Bit 8
Bit 0
Bit 0
0
0