MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 155

IC MCU 32K FLASH 8MHZ 80-QFP

MCHC912B32CFUE8

Manufacturer Part Number
MCHC912B32CFUE8
Description
IC MCU 32K FLASH 8MHZ 80-QFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MCHC912B32CFUE8

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
63
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
768 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Cpu Family
HC12
Device Core Size
16b
Frequency (max)
8MHz
Interface Type
SCI/SPI
Total Internal Ram Size
1KB
# I/os (max)
63
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Package
80PQFP
Family Name
HC12
Maximum Speed
8 MHz
Operating Supply Voltage
5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
63
Processor Series
HC912B
Core
HC12
Data Ram Size
1 KB
Maximum Clock Frequency
8 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912B32E
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCHC912B32CFUE8
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MCHC912B32CFUE8
Quantity:
300
12.3.15 Data Direction Register for Timer Port
Read: Anytime
Write: Anytime
The timer forces the I/O state to be an output for each timer port pin associated with an enabled output
compare. In these cases the data direction bits will not be changed, but they have no affect on the
direction of these pins. The DDRT will revert to controlling the I/O direction of a pin when the associated
timer output compare is disabled. Input captures do not override the DDRT settings.
12.4 Timer Operation in Modes
Stop — Timer is off since both PCLK and ECLK are stopped.
BDM— Timer keeps running, unless TSBCK = 1.
Wait — Counters keep running, unless TSWAI = 1.
Normal — Timer keeps running, unless TEN = 0.
TEN = 0 —All timer operations are stopped, registers may be accessed.
Gated pulse accumulator ÷64 clock is also disabled.
PAEN = 0 —All pulse accumulator operations are stopped.
Registers may be accessed.
Freescale Semiconductor
0 = Configures the corresponding I/O pin for input only
1 = Configures the corresponding I/O pin for output
Address: $00AF
Reset:
Read:
Write:
Figure 12-29. Data Direction Register for Timer Port (DDRT)
DDT7
Bit 7
0
DDT6
6
0
M68HC12B Family Data Sheet, Rev. 9.1
DDT5
5
0
DDT4
4
0
DDT3
3
0
DDT2
2
0
DDT1
1
0
Timer Operation in Modes
DDT0
Bit 0
0
155

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