ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 77

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Bin):
Bit #
Bit #
Bit #
11:0
15:8
1:0
4:1
15
14
13
13
12
1. Unassigned Cells have a fixed header corresponding to 00000000 00000000 00000000 0000xxx0.
2. Idle Cells have a fixed header corresponding to 00000000 00000000 00000000 00000001.
7
6
5
0
Type
Type
Type
ROL
ROL
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R
R
R
Indicates that the parity error counter has rolled-over. This is a sticky bit which is set by
the hardware and reset by the user (by writing ’0’ to this bit).
Indicates that at least one parity error has occurred since this register was reset. This is a
sticky bit which is set by the hardware and reset by the user (by writing ’0’ to this bit.
When written with a 1 the internal TX UTOPIA Parity Error Counter value will be
transferred to the lower 12 bits of this register. When written with ’0’, no transfer is done.
Reading a 1 in this register indicates that the TX UTOPIA Parity Error Counter has been
updated. Reading a 0 indicates that the register is not updated yet.
When this bit is set the TX UTOPIA Parity Error Counter will be reset. When this bit is
reset the TX UTOPIA Parity Error Counter will operate normally.
TX UTOPIA Parity Error Counter. These bits contain the value of the TX UTOPIA Parity
Error Counter. The counter must be loaded into the register using bit 13.
Unused. Read all 0’s.
Status Bit. Goes to 0 during initialization and returns to 1 on completion of initialization.
Write 1 to this bit for normal operation. Write 0 in conjunction with bit 0 to initialize the TX
Cell RAM; otherwise, write 1.
Reserved. Write 0 for normal operation.
Reserved. Write 0’s for normal operation.
Reserved. Write 0 to initialize the internal Cell RAM.
HEC Verification.
11: Enable HEC error correction if 1 bit is wrong, discard cell if more than 1 bit are wrong.
10: Discard cell if HEC is wrong, no HEC correction.
01: Enable HEC error correction if 1 bit is wrong, no correction if more than 1 bit wrong,
cell is not discarded if HEC is wrong.
00: No verification of HEC.
used.
0x0053 (1 reg)
1 register to contain information about parity errors on the Tx UTOPIA data bus.
0000
0x0052 (1 reg)
1 register for all the UTOPIA Input ports.For ZL30226 groups 0, 1, 2 and 3 are
000X000000000000
0x0080 (1 reg)
Used for initialization of the internal TX Internal Cell RAM (Filler, Idle Cells, etc.)
000000001X000000
Table 15 - UTOPIA Input Control Register (continued)
Table 16 - UTOPIA Input Parity Error Register
Table 17 - TX Cell RAM Control Register
Zarlink Semiconductor Inc.
ZL30226/7/8
77
Description
Description
Description
Data Sheet