ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 58

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

The device will not accept a cell from the UTOPIA Interface if the internal Cell Ram is full. Status bit 0 in the
General Status (0x040E) register is set to 1 to indicate the ’no free cell in TX Cell RAM’ condition. The status
bit can be cleared by overwriting it with 0.
Note that the internal FIFO level on the TX direction is updated after the complete cell is received. If the
corresponding Utopia port address is poled, that the Cell Available Status signal could reflect space available
whereas the FIFO should be reported full. If a cell transfer is initiated under these conditions, the cells will be
accepted and the next time the Utopia port is polled, the Cell Available Status signal will report the correct state of
the FIFOs.
The UTOPIA Input block has the option to verify the HEC of the cell coming from the ATM layer. Four different options
are available and are selected by bits 1 and 0 of the UTOPIA Input Control (0x0052) register.
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5.2
The ZL30226/7/8 supports a 53 byte/27 word cell stream via the ATM output port. Cells received at the ATM output
port are stored in the RX UTOPIA FIFO before being processed by the UTOPIA Interface. The output of the UTOPIA
Interface can be stopped by the ATM Layer device by de-asserting the RxENB* signal.
The start of a cell is marked with the SOC signal, which is active during the transmission of the first byte/first word
of a cell. The following 52 bytes/26 words are belonging to the same cell.
The RX byte clock (RxClk) can be up to 52 MHz and is checked against the system clock. If the incoming byte clock
frequency is lower than 1/128 of the system clock, bit 3 of the General Status (0x040E) register will be set. This bit
is cleared by overwriting it with 0. This aids in debugging as the presence of a UTOPIA clock is required not
only for data transfer but also for proper operation of the UTOPIA registers.
Overflow conditions in the RX UTOPIA FIFO associated with any of the 24 PHY RX Addresses cause a status bit to
be set in either the IRQ Link TC Overflow Status (0x0410-0x041F) or IRQ IMA Overflow Status Registers
(0x0420-0x0427) register. These status bits are cleared by overwriting them with 0. Additionally, for each status
bit there is an Interrupt Enable bit in the associated IRQ Link TC Overflow Enable (0x0434) or RX UTOPIA IMA
Group FIFO Overflow IRQ Enable (0x040C) register. When enabled, the status bit is reported in an Interrupt
register. See section 6.2 Interrupt Block for more details.
The size of the RX UTOPIA FIFO is fixed at four cells for the TC PHY Addresses and four cells for the IMA Group
PHY Addresses.
Note that in the receive direction, the parity bit that is generated is not valid if the receive Utopia clock is faster than
50 MHz.
The ’00’ option is used to always accept a cell from the ATM layer. The HEC is verified and if wrong, the
UTOPIA Input counter associated with the UTOPIA port for cells with bad HEC is incremented. The
ZL30226/7/8 will re-generate a valid HEC based on the content of the 4-byte header that was received.
The ’01’ option is used to verify the HEC of an incoming cell. If the HEC value is wrong and if it can be
corrected (1 bit error), then the cell is corrected and accepted as a good cell. The bad HEC counter is not
incremented if the HEC is corrected. The bad HEC counter is incremented if the HEC value cannot be
corrected. In this mode, the cell is always accepted. The ZL30226/7/8 will re-generate a valid HEC based on
the content of the 4-byte header that was received.
The ’10’ option is used to verify the HEC on the incoming cell and discard the cell if the HEC value is wrong.
The bad HEC counter is incremented if a cell is discarded.
The ’11’ option is similar to mode ’01’ except that if the HEC value cannot be corrected, then the cell is
discarded. If the HEC value is corrected, the bad HEC counter is not incremented.
ATM Output Port
Zarlink Semiconductor Inc.
ZL30226/7/8
58
Data Sheet