ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 55

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

This mode is selected in TDM TX Link Control (0x0600-0x060F) and TDM RX Link Control (0x0700-0x070F) by
writing the following settings into those enabled links only.
4.2
The TXCK signal can be programmed to be either output or input.
In the generic modes, the clock polarity can be selected to have a rising or falling edge at the bit boundary.
4.3
Two loopback modes are provided where the TDM RX inputs are internally routed back to the TDM TX outputs
(remote loopback) with the RX block fully operational, and where the TDM TX outputs are routed back to the TDM
RX inputs for test purposes (metallic loopback). The TX and RX links have to be programmed in the same mode for
the loopback to operate properly. Bit 8 of the TDM TX Link Control Register (0x0600-0x060F) controls the remote
loopback and bit 8 of the TDM RX Link Control (0x0700-0x070F) register controls the metallic loopback.
To use remote loopback, TXCK must be configured as output sourcing from the RXCK of the same port. The
loopback is on a per link basis with the limitation that physical links are paired: i.e. TX link 0 is connected to RX link
0 and so on.
Besides TDM loopacks, there is also a UTOPIA loopback described in the section 5.7.
4.4
Each serial TDM link has assigned S/P and P/S units. The P/S unit takes a byte from the cell RAM and converts it
to a serial bit stream. The S/P unit takes a byte from the DSTi input and converts it to parallel format for use by the
Cell Delineation block.
P/S and S/P units can be set-up differently on a per port and per direction basis (i.e. the transmit and receive function
of the same port can use different configurations). The following features are supported:
•
•
•
When the TXCK signals are outputs, the source for the TXCLK is software selectable from any of the RXCK inputs
or any of the four external REFCKs.
4.5
TXCK can be either input or output signal. When TXCK are inputs, they are generated by external circuitry. When
TXCK are outputs, TXCK source is software selectable and can be any of the RXCK signals or four external REFCK
inputs (see Figure 11).
The RXCK pins are always defined as inputs and the proper signal must be provided to each input.
enabling/disabling the P/S and S/P units (if they are disabled the associated outputs are Tri-stated)
independently programming the polarity of RXCK and TXCK signals (Generic TDM mode only)
generating/accepting TXCLK signals to support most xDSL framers (depending on the programmed mode)
Clock format
TDM Loopback Mode
.Serial to Parallel (S/P) and Parallel to Serial (P/S) Converters
Clocking Options
Data rate (bits 6:5) = 11
Multiplex mode (bits 4:3) = 00
Cell delineation mode (bit 10 of TDM RX Link Control only) = 1
Zarlink Semiconductor Inc.
ZL30226/7/8
55
Data Sheet