ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 17

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

ZL30226 Pin Description (continued)
P2,T3,Y2,AB3,
D13,D17,N23,
N25,H26,F26,
A23,D20,C16,
E2,H1,J1,M3,
D6,D10,D14,
AD12,AD15,
AC19,AD25,
AC06,AC13,
AC17,AC22,
D22,E23,F4,
K23,N4,P23,
AC16,AE16,
AF16,AC15,
AA23,AB04,
AC14,K4,P4
AE15,AF15,
AD14,AE14
A13,A8,C5
U23,AC10,
AA25,V26,
AE6,AF8,
Pin #
AC1
AD1
C19
D19
A4
D7
A5
B6
C6
B5
C7
B4
U4
Data[7:0]
LatchClk
RXRing
Name
Reset
TRST
VDD5
Test1
Test2
Test3
Test4
TMS
TDO
TCK
V3.3
V2.5
TDI
Clk
I/O
O JTAG Test Data Output. Note: TDO is tristated by TRST pin.
O Test2. Must be left not connected (NC).
O Test4. Must be left not connected (NC)
S 5 Volt supply pin. Connect to a 5 volt supply when interfacing to 5 volt signals,
S 3.3 Volt supply pin for I/O pins. Connect to a 3.3 Volt supply.
S 2.5 Volt supply for core. Connect to a 2.5 Volt power supply.
I
I
I
I
I
I
I
I
I
I
TDM Ring RX Data[7:0]. Data Bus connecting the RX TDM Ring port to the TX
TDM Ring port. Should be connected to the TXRingData inputs of the previous
ZL30226 device in the Ring. There are internal weak pull-downs on these
inputs.
System Clock (50 MHz nominal). In the ZL30226, this clock is used for all
internal operations of the device.
Counter Latch Clock. The clock present at this input can be divided internally
to produce the latch signal for the internal counters. Refer to the Counter
Transfer Command register for more details. This pin has an internal
pull-down.
System Reset. This is an active low input signal. It causes the device to enter
the initial state. The Clk signal must be active to reset the internal registers.
JTAG Test Clock. TCK should be pulled down if not used.
JTAG Test Mode Select. TMS is sampled on the rising edge of TCK.
JTAG Test Data Input. This pin has an internal weak pull-down.
JTAG Test Reset (active low). Should be asserted LOW on power-up and
during reset. Must be HIGH for JTAG boundary-scan operation. This pin has an
internal weak pull-down.
Test1. Must be tied Low
Test3. Must be pulled up to V3.3 for normal operation. NOT 5 V TOLERANT.
otherwise, connect to a 3.3 Volt supply.
Zarlink Semiconductor Inc.
ZL30226/7/8
System Signals
Power Signals
17
Description
Data Sheet