ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 68

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

When the new byte is different, a copy of the new byte along with the byte number is put into a dedicated
preprocessor FIFO, accessible via the Processed RX Cell Link FIFO (0x0140 - 0x014F) registers. There is one
preprocessor FIFO (circular buffer) of 64 entries per RX Link. Each FIFO entry is 16-bits wide and the ZL30226/7/8
increments automatically the internal pointer to point to the next entry for the next read access. The Least Significant
Byte (bits 7 to 0) contains the newly received byte that was found to be different. Bits 13 to 8 contain the byte position
in the ATM Cell. The numbering scheme goes from byte #1 to byte #53. The bit 14 is used as a flag to indicate the
last byte that was found to be different in the newly received ATM cell that was put in the RX Cell buffer. Bit 15 is
used to indicate if there are more bytes in the FIFO. A value of "0" indicates the last valid byte (the FIFO is empty)
and a value of "1" indicates that there are more bytes to be read. See below for a representation of a word read from
the FIFO.
When the pre-processing option is enabled, (using the RX Cell Processor Enable register), the IRQ normally
generated to indicate that a new cell was put in the RX Cell buffer is re-defined to indicate that the compare process
has been complete and that the bytes that were found to be different are available for the software to access, in the
link Preprocessor FIFO.
For each link, the FIFO is 64 words deep to accommodate up to 64 preprocessed bytes (bytes that were found to be
different). The bytes in the FIFO can be from different preprocessed cells.
Whenever bit 14 of the word read from the FIFO is set, indicating the last byte of an ATM cell, the software has to
check the level of bit 15 to determine if there are more bytes to be read from other processed cells on the same link.
If there are no more bytes, then the software should start polling the status bit (empty/not empty) and/or wait for an
IRQ before reading the FIFO. To facilitate this task, associated with the RX Cell FIFOs, the Processed RX Cell Link
FIFO Status register (0x107) reports if a FIFO is empty or not empty. Each bit in the register is reflecting the status
of one of the sixteen links.
When the preprocessing option is not enabled, the RX Cell buffers operate the same way as in the MT90220/221.
All 53 bytes from the ATM Cell are accessible when the preprocessing mode is disabled.
6.5
The TDM Ring Block is typically used to form IMA groups that source their links from more than one ZL30226/7/8.
All ZL30226/7/8 devices in the TDM Ring must operate synchronously, with the same system clock. This system
clock needs to be the identical in frequency but not necessarily phase aligned.
The TDM Ring is located between the TDM Serial Interface (S/P converters) and the internal Transmission Control
(TC) / IMA blocks (see figures 5 and 7). This bus allows links to be routed from one ZL30226/7/8 to other
ZL30226/7/8s as if the link was internally sourced, limited by the ZL30228’s link capacity of 16 links (8 links on the
ZL30227 and 4 links on the ZL30226) and the TDM Ring capacity of 32 links.
TDM Ring Block
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Processed RX Cell FIFO Word Format
Figure 16 - Processed RX Cell FIFO Word Format
Zarlink Semiconductor Inc.
ZL30226/7/8
68
Byte content from the latest RX Cell
Position in Cell for the byte found to be
different (number range between 1 and 51)
When set, indicates the last byte reported
for the current processed cell.
When clear (0), indicates that the FIFO associated with
this link is empty (no more bytes to be read)
Data Sheet