ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 113

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Bit #
Bit #
Bit #
15:0
15:0
6:5
4:3
9
8
7
2
1
0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
Type
R/W
R/W
Clock direction
When 0, TXCK is output.
When 1, TXCK is input.
Remote Loopback
When 1, TXCK and DSTo come from the RX pins of the same link.
When 0. normal mode.
Link enable
When 0, the TX port is in high impedance mode
When 1, the TX port is active
Data rate: Bits 4:3 must be 00
11: 10.0 Mb/sec. (Only links 0, 4, 8 and12 can be used)
10: 5.0 Mb/sec. (Only links 0, 2, 4, 6, 8, 10 and 12 can be used)
01: 2.5 Mb/sec
00: Reserved
Reserved:
Write 00 for normal operation
Reserved:
Write 0 for normal operation
Clock polarity:
When 0, the data is output/sampled at the falling edge of TXCK
When 1, the data is output/sampled at the rising edge of TXCK
Reserved:
Write 1 for normal operation
Write all 1’s for normal operation.
Write all 1’s for normal operation.
0x0600 - 0x060F (16 reg)
1 reg. per TX link.
0000
0x0610 - 0x061F (16 reg)
Control time slot 15:0.
0000
0x0620 - 0x062F (16 reg)
Control time slot 31:16.
0000
Table 101 - TDM TX Mapping (timeslots 31:16) Register
Table 100 - TDM TX Mapping (timeslots 15:0) Register
Table 99 - TDM TX Link Control Register (continued)
(All links are available)
Zarlink Semiconductor Inc.
ZL30226/7/8
113
Description
Description
Description
Data Sheet