ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 106

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Synchronized access
Reset Value (Hex):
15:13
Bit #
Bit #
9:8
1:0
12
10
10
11
9
8
7
6
7
6
5
4
3
2
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Unused. Read all 0’s.
This bit is set when the RX UTOPIA FIFO associated with a Link in non-IMA mode
overflows. This bit is cleared by writing 0.
This bit is set when the UTOPIA Input counter for all cells (or all Stuff cells event)
associated with a link used in non-IMA mode overflows. This bit is cleared by writing 0.
This bit is set when the UTOPIA Input counter for Idle Cells associated with a link used in
non-IMA mode overflows. This bit is cleared by writing 0.
This bit is set when the UTOPIA Input counter for Unassigned Cells associated with a link
used in non-IMA mode overflows. This bit is cleared by writing 0.
This bit is set when the UTOPIA Input counter for HEC Errored Cells associated with a
link used in non-IMA mode overflows. This bit is cleared by writing 0.
This bit is set when the TX TDM Link counter for all cells associated with a link overflows.
This bit is set when the TX TDM Link counter for Idle or Filler Cells associated with a link
overflows.
Counter values are latched when this bit is changed from 0 to 1 and bit 9:8 are set to 11.
Writing 0 has no effect.
Write 00 for normal operation without using the latch made.
Write 01 to latch the counter value at every rising edge of the signal at LatchClk pin.
Write 10 to latch the counter value every 8000 rising edges of the signal at LatchClk pin.
Write 11 to latch the counter value every time bit 10 of this register is written to 1.
Write: 0 for normal operation.
Read: 1 when the transfer is done, 0 when the transfer is pending.
Toggle bit. Toggles with every write access to ZL30226/7/8.Write 0 for normal operation.
Reserved. Write 0 for normal operation. Read value is undetermined.
Reserved. Write 0 for normal operation.
Value to write to the Enable bit. 1 to enable, 0 to mask interrupt. This value is transferred
when the bit 1:0 are 10.
0 will enable the transfer from the uP to the selected counter.
1 will enable the transfer from the selected counter to the uP.
00: Initialize all the counters with 0.
01: Initiate a read or write of the counter value.
10: Initiate a read or write of the IRQ enable counter bit.
11: Unused.
Table 86 - Counter Transfer Command Register (continued)
0x0410 - 0x041F (16 reg)
1 register per link. The RxClk and TxClk signals must be active for correct
register operation.
0000
0x040F (1 reg)
0080
Table 87 - IRQ Link TC Overflow Status Registers
Zarlink Semiconductor Inc.
ZL30226/7/8
106
Description
Description
Data Sheet