ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 16

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

ZL30226 Pin Description (continued)
B17,C17,A18,
B18,D18,C18,
AA3,AA4,
AB2,AB1
A19,B19
AA1,Y3
AE21,
AA26,
AF21,
AD17
Pin #
AF17
AF13
AF14
U25,
G25,
U24,
C23,
Y23,
A25,
L24,
L25,
G26,
B20
C20
D16
A17
RXRingClk
TXRingClk
Data[7:0]
PLLREF
TXCKio
RXRing
REFCK
TXRing
TXRing
RXCKi
Name
DSTo
Sync
Sync
DSTi
[1:0]
[3:0]
[12]
[12]
[12]
[12]
[8]
[4]
[0]
[8]
[4]
[0]
[8]
[4]
[0]
[8]
[4]
[0]
I/O
I/O TDM Interface Transmit Clock 12, 8, 4, and 0. This pin is an input or an output
O Serial TDM Data Output 12, 8, 4, and 0. Serial stream which contains transmit
O Output reference to an external PLL.
O TDM Ring TX Clock. Clock output signal used to align the TXRingSync and
O TDM Ring TX Sync. Synchronization output signal used to retrieve data and
O TDM Ring TX Data[7:0]. Data Bus connecting the TX TDM Ring port to the RX
I
I
I
I
I
data. The output is set to high impedance for unused time slots and if the link is
not used. It is aligned with TXCKio.
Serial TDM Data Input 12, 8, 4, and 0. Serial stream which contains receive
data. It is aligned with RXCKi. These pins have internal weak pull-downs.
as selected by the TDM TX Link Control registers. The TXCK source is
software selectable and can be either one of the four RXCK or one of the four
REFCK signals when defined as output. When defined as input, the proper
clock signal is provided to the input pin. The clock polarity is determined by the
TDM TX Link Control registers. These pins have internal weak pull-downs.
TDM Interface Receive Clock 12, 8, 4, and 0. This input line represents the
clock for the receive serial TDM data. The expected frequency value to be
received at this input clock is defined by the user through the RX Link TDM
Control register. These pins have internal weak pull-downs.
Input Reference Clock inputs 3 to 0. Receive the de-jittered transmit clock
reference to be internally routed to the TXCKio transmit clocks. These pins have
internal weak pull-downs.
TXRingData. Should be connected to the RXRingClk input of the next ZL30226
device in the Ring. This output is in High Z state if the TDM Ring is not used.
control from the bytes on TXRingData. Should be connected to the RXRingSync
input of the next ZL30226 device in the Ring. This output is in High Z state if the
TDM Ring is not used.
TDM Ring port. Should be connected to the RXRingData inputs of the next
ZL30226 device in the Ring. These output are in High Z state if the TDM Ring is
not used.
TDM Ring RX Clock. Clock input signal used to align the RXRingSync and
RXRingData. Should be connected to the TXRingClk input of the previous
ZL30226 device in the Ring. There is an internal weak pull-down on this input.
TDM Ring RX Sync. Synchronization input signal used to retrieve data and
control from the bytes on RXRingData. Should be connected to the TXRingSync
output of the previous ZL30226 device in the Ring. There is an internal weak
pull-down on this input.
TDM Interface Signals
Zarlink Semiconductor Inc.
TDM Ring Signals
ZL30226/7/8
16
Description
Data Sheet