ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 28

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

ZL30228 Pin Description (continued)
U25,V24,W25,
P26,M26,M24,
U24,V23,W24,
H25,G26,G24,
P25,N24,M23,
P24,R23,T23,
H23,G25,F25,
E26,C26,A25,
B23,A22,B21,
F24,E24,C23,
A24,B22,D21,
R26,T26,T24,
L24,K24,J23,
L25,K25,J25,
AB26,AC26,
AC24,AE21,
AE20,AE19,
AB25,AC25,
AE22,AF21,
AF20,AF19,
AC18,AD17
AE18,AF17
Y25,AA26,
AA3,AA4,
Y26,Y23,
AB2,AB1
AA1,Y3
Pin #
AE13
AC9
B20
C20
D16
A17
TXRingSync
TXRingClk
PLLREF
TXCKio
REFCK
RXCKi
Name
up_irq
up_cs
DSTo
[15:0]
[15:0]
[15:0]
[15:0]
DSTi
[1:0]
[3:0]
I/O
I/O TDM Interface Transmit Clock 15-0. This pin is an input or an output as
O Processor Interrupt Request. Open drain signal. If this signal is low, the
O Serial TDM Data Output 15-0. Serial stream which contains transmit data.
O Output reference to an external PLL.
O TDM Ring TX Clock. Clock output signal used to align the TXRingSync and
O TDM Ring TX Sync. Synchronization output signal used to retrieve data and
I
I
I
I
Chip Select. This is an active low input signal. If this signal is high, the
ZL30228 ignores all other signals on its processor bus. If this signal is low, the
ZL30228 accepts the signals on its processor bus.
ZL30228 signals to the processor that an interrupt condition is pending inside
the ZL30228.
The output is set to high impedance for unused time slots and if the link is not
used. It is aligned with TXCKio.
Serial TDM Data Input 15-0. Serial stream which contains receive data. It is
aligned with RXCKi. These pins have internal weak pull-downs.
selected by the TDM TX Link Control registers. The TXCK source is software
selectable and can be either one of the sixteen RXCK or one of the four
REFCK signals when defined as output. When defined as input, the proper
clock signal is provided to the input pin. The clock polarity is determined by the
TDM TX Link Control registers. These pins have internal weak pull-downs.
TDM Interface Receive Clock 15-0. This input line represents the clock for
the receive serial TDM data. The expected frequency value to be received at
this input clock is defined by the user through the RX Link TDM Control
register. These pins have internal weak pull-downs.
Input Reference Clock inputs 3 to 0. Receive the de-jittered transmit clock
reference to be internally routed to the TXCKio transmit clocks. These pins
have internal weak pull-downs.
TXRingData. Should be connected to the RXRingClk input of the next
ZL30228 device in the Ring. This output is in High Z state if the TDM Ring is
not used.
control from the bytes on TXRingData. Should be connected to the
RXRingSync input of the next ZL30228 device in the Ring. This output is in
High Z state if the TDM Ring is not used.
TDM Interface Signals
Zarlink Semiconductor Inc.
TDM Ring Signals
ZL30226/7/8
28
Description
Data Sheet