ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 126

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

ZL30226/7/8
Data Sheet
8.1
CPU Interface Timing
The CPU Interface of the ZL30226/7/8 supports both the Motorola and Intel timing modes. No Mode Select pin is
required.
With Motorola devices, the Motorola R/W-signal is connected to the UP_R/W pin and the UP_OE pin is tied to
ground. There is no DS signal and the UP_CS signal is taken to access the ZL20226/227/228.
When used with Intel devices, the READ-signal is connected to the UP_OE pin and the WRITE-signal is connected
to the UP_R/W pin.
When performing a read operation, data is placed on the bus immediately after UP_CS is lLOW and UP_R/W is
HIGH for the Motorola timing mode and after the UP_CS and UP_OE signals are LOW for Intel timing.
When performing a write operation in Motorola timing mode, the data is clocked into an ZL30226/7/8 pre-load
register upon the first rising edge of UP_R/W or UP_CS signals. In Intel timing mode, the data is clocked into
ZL30226/7/8 pre-load register upon the first rising edge of UP_R/W or UP_CS signals. Right after that transition,
the data is transferred to the ZL30226/7/8’s internal register. Writing data into this register can take up 2 system
clock cycles.
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Zarlink Semiconductor Inc.