ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 13

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Diagram - ZL30228
The ZL30228 uses a 384 pin PBGA with a 1.0 mm ball pitch.
AA
AB
AC
AD
AE
AF
G
M
W
A
B
C
D
E
F
H
J
K
L
N
P
R
T
U
V
Y
DSTi[5]
DSTi[6]
TXCKio
TXCKio
TXCKio
RXCKi
VDD5 DSTi[7] RXCKi
VDD5
VDD5
DSTo
DSTo
DSTo
DSTi
DSTi
[14]
[15]
[15]
[14]
NC
PD
PD
PD
NC
26
[8]
[9]
[8]
[7]
[6]
26
IC
IC
IC
IC
IC
DSTi[4] RXCKi
DSTi[8] RXCKi
TXCKio
TXCKio
TXCKio
RXCKi
RXCKi
RXCKi
RXCKi
RXCKi
VDD5
DSTo
DSTo
VDD5
VDD5
VSS
VSS
[10]
[11]
[12]
[15]
[12]
[10]
NC
NC
PD
PD
PD
NC
25
[9]
[9]
[7]
[6]
25
IC
IC
TXCKio
TXCKio
TXCKio
RXCKi
RXCKi
DSTo
DSTo
DSTo
DSTi
DSTi
DSTi
VSS
VSS
[11]
[12]
[13]
[14]
[15]
[13]
[12]
[11]
[10]
NC
NC
PD
PD
PD
NC
NC
24
[3]
IC
[5]
[6]
[7]
IC
IC
[5]
24
TXCKio
DSTi[3] RXCKi
DSTi[9]
RXCKi
RXCKi
VDD5 DSTi[2]
DSTo
DSTo
DSTo
V3.3
DSTi
V3.3
V2.5
V3.3
V2.5
V3.3
VSS
VSS
VSS
[10]
[13]
[14]
[13]
[11]
23
NC
PD
NC
NC
NC
23
[4]
IC
IC
[8]
TXCKio
V3.3
V3.3
22
NC
NC
22
[2]
IC
[5]
TXCKio
DSTi[1] DSTi[0] TXRing-
RXCKi
DSTo
NC
21
PD
21
IC
IC
[1]
[4]
[4]
TXCKio
RXCKi
VDD5
DSTo
NC
PD
20
[0]
[3]
[3]
20
IC
TXRing-
TXCKio
Data[1]
Data[0]
Latch
VDD5
DSTo
Test2 TXRing-
Clk
PD
19
[2]
[2]
19
Figure 4 - ZL30228 Pinout (Bottom View)
TXRing-
TXRing-
TXRing-
Data[5]
Data[4]
Data[2]
Data[3]
TXCKio
DSTo
PD
PD
18
[1]
[1]
18
TXRing-
TXRing-
TXRing-
TXCKio
Data[7]
Data[6]
DSTo
Sync
V2.5
V3.3
17
NC
17
[0]
[0]
TXRing-
sr_cs_1 sr_a[1] sr_a[4]
sr_cs_0 sr_a[0] sr_a[3] sr_a[5] sr_a[8]
RXRing
RXRing
RXRing
Data[7]
Data[6]
Data[5]
VDD5
VSS
VSS
VSS
VSS
VSS
VSS
Zarlink Semiconductor Inc.
Clk
16
PD
16
ZL30226/7/8
RXRing
RXRing
RXRing
Data[4]
Data[3]
Data[2]
sr_we
VDD5 RXRing
VSS
VSS
VSS
VSS
VSS
VSS
NC
15
15
RXRing
RXRing
sr_a[2] sr_a[6]
Data[1]
Data[0]
Sync
V3.3
VSS
VSS
VSS
VSS
VSS
VSS
V2.5
14
14
13
or up_rd
RXRing
up_oe
VDD5
up_cs
V2.5
VSS
VSS
VSS
VSS
VSS
VSS
V3.3
Clk
13
13
sr_a[7]
sr_a[9]
up_r/w
VDD5 up_a[6] up_a[3] up_a[0]
up_wr
up_a
up_a
sr_a
VSS
VSS
VSS
VSS
VSS
VSS
[10]
[10]
[11]
12
12
or
up_a[7]
up_a[8] up_a[4] up_a[1]
up_a[9] up_a[5] up_a[2] VDD5
sr_a
sr_a
sr_a
sr_a
VSS
VSS
VSS
VSS
VSS
VSS
[11]
[12]
[14]
[13]
11
11
V3.3
V2.5
sr_a
sr_a
sr_a
[15]
[16]
[17]
10
10
sr_d[0] sr_d[3] sr_d[7]
sr_d[2] sr_d[5]
up_irq
sr_a
sr_d
[18]
[1]
9
9
sr_d[4]
VDD5
up_d
up_d
[14]
[15]
NC
8
8
sr_d[6]
Test3
up_d
up_d
up_d
up_d
TCK
[10]
[11]
[12]
[13]
7
7
up_d[8] up_d[5] up_d[2]
up_d[9] up_d[7]
VDD5 up_d[6] up_d[4] up_d[1]
TDO
V3.3
V3.3
TDI
NC
6
6
VDD5
TRST
TMS
VSS
VSS
5
5
REFCK
Data[0]
Data[9]
UTxClk
Addr[2]
Addr[4]
ata[10]
ata[14]
ata[13]
Reset
URxD
URxD
URxA
Test4
ddr[2]
UTxD
V3.3
SOC
V2.5
V3.3
V2.5
V3.3
V3.3
VSS
VSS
URx
UTx
UTx
UTx
UTx
VSS
NC
NC
[2]
4
4
UTxPar UTxD
REFCK
REFCK
Data[1]
Data[5]
Data[7]
Data[2]
Data[6]
Addr[3]
up_d[3] up_d[0]
ata[11]
ata[15]
ata[10]
URxD
URxD
URxA
ddr[1]
VDD5
UTxD
VDD5
VDD5
URx-
VSS
Clav
VSS
URx
URx
URx
URx
CLK
UTx
UTx
UTx
Enb
UTx
NC
NC
NC
[0]
[3]
3
3
Data Sheet
Data[0]
Data[3]
Data[8]
ata[12]
Data[1]
Data[3]
ata[12]
ata[15]
Addr[1]
REF[1]
VDD5
URxD
URxA
ddr[3]
VDD5
UTxD
ata[8]
UTxD
VDD5
VSS
URx
URx
URx
URx
URx
Clav
VSS
Enb
UTx
UTx
UTx
UTx
PLL
NC
Par
NC
NC
NC
NC
2
2
REFCK
Data[2]
Data[4]
Data[6]
Data[9]
ata[13]
Data[4]
Data[5]
ata[14]
Addr[0]
REF[0]
ata[11]
URxD
VDD5
VDD5
URxA
ddr[0]
URxA
ddr[4]
UTxD
ata[7]
UTxD
UTxD
SOC
Test1
URx
URx
URx
URx
UTx
UTx
UTx
UTx
PLL
NC
NC
NC
Clk
NC
[1]
1
1
AA
AB
AC
AD
AE
AF
W
A
B
C
D
E
G
H
K
M
N
P
R
U
V
Y
F
J
L
T