ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 121

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Note 1: Greater than 50 MHz operation is possible with less than worst case duty cycle, jitter and rise/fall times such as 52 MHz
operation with 45/55% (or better) duty cycle and 2.5% (or better) jitter.
Note 1: Greater than 50 MHz operation is possible with less than worst case duty cycle, jitter and rise/fall times such as 52 MHz
operation with 45/55% (or better) duty cycle and 2.5% (or better) jitter.
Note 2: URxPAR is not valid for cases where URxClk low pulse is shorter than 7.9 nsec.
AC Electrical Characteristics - UTOPIA Interface Receive Timing (≤ 50 MHz)
- Multi-PHY operation with up to 4 input loads of 10 pF each (40 pF total).
AC Electrical Characteristics - Utopia Interface Transmit Timing (≤ 50 MHz)
- Multi-PHY operation with up to 4 input loads of 10 pF each (40 pF total).
URxClk
URxEnb, URxAddr[4:0]
URxData[15:0], URxSOC,
URxClav[0], URxPAR
UTxClk
UTxData[15:0], UTxSOC,
UTxPAR, UTxEnb,
UTxAddr[4:0]
UTxClav[0]
Signal name
Signal name
2
A->P
A->P
A<-P
DIR
A->P
A->P
A<-P
DIR
Item
tT10
tT12
tT11
tOD
tT2
tT3
tT4
tT5
tT6
tT8
tT9
f1
f1
Item
tT10
tT11
tT12
tOD
tT2
tT3
tT4
tT5
tT6
tT8
tT9
Zarlink Semiconductor Inc.
TxClk frequency nominal (8-bit UTOPIA)
TxClk frequency nominal (16-bit UTOPIA)
TxClk duty cycle
TxClk peak-to-peak jitter
TxClk rise/fall time
Input setup to TxClk
Input hold from TxClk
Output delay from TxClk
Output hold from TxClk
Signal going low impedance to TxClk
Signal going high impedance to TxCLK
Signal going low impedance from TxClk
Signal going high impedance from TxClk
f1
ZL30226/7/8
RxClk frequency (nominal)
RxClk duty cycle
RxClk peak-to-peak jitter
RxClk rise/fall time
Input setup to RxClk
Input hold from RxClk
Output delay from RxClk
Output hold from RxClk
Signal going low impedance to RxClk
Signal going high impedance to RxClk
Signal going low impedance from
RxClk
Signal going high impedance from
RxClk
121
Description
Description
1
1
Min.
40%
4 ns
1 ns
1 ns
4 ns
0 ns
1 ns
1 ns
Min.
40%
4 ns
1 ns
1 ns
4 ns
0 ns
1 ns
1 ns
0
0
-
-
-
0
-
-
-
Data Sheet
50 MHz
33 MHz
50 MHz
14 ns
Max.
14 ns
60%
Max.
2 ns
60%
2 ns
5%
5%
-
-
-
-
-
-
-
-
-
-
-
-
-
-