ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 69

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Operation of the TDM Ring is programmed via 16 Ring Tx Link (0x0181-0x0190) registers, 16 Ring Rx Link
(0x01C0-0x01CF) registers and one Ring Tx Control (0x0180) register.
The Ring Tx Control (0x0180) sets which ZL30226/7/8 is the master (source of the TDM Ring clock) and whether
the TDM Ring is active (not tri-stated). There can be only one TDM Ring master in a single ring. A link is then placed
on the ring by associating it with one available time slot and then retrieved off the ring by referencing the same time
slot.
See Technical Note TN90224.1 for more information.
6.6
The SRAM decoding block has a feature that allows more efficient external SRAM memory utilization when only 8
or 4 TDM links are used. This is particularly pertinent to the ZL30227 and ZL30226.
SRAM address decoding is based in part on the link number. Since the ZL30227 and ZL30226 use only even
numbered links, normal decoding would result in half the memory not being used. The following method describes
how to more fully utilize one external SRAM component rather than using two external SRAM components, thus
achieving the same differential link delay capacity with reduced board space and cost.
With only one external SRAM physically connected, set bit 0 of the SRAM Control (0x0299) register to use two
banks of memory. Additionally, set bit 8 of the same register to remap SRAM Chip Select 1 (
unused address line. This combination of using two logical memory banks with chip select remapping will achieve
the desired efficient use of a single external SRAM component.
7.0
Throughout the following register descriptions, it should be noted that only the registers and register bits
corresponding to available links are meaningful. Registers and register bits corresponding to unavailable links should
be masked or otherwise ignored. The ZL30228 has links 0:15. The ZL30227 has links 0, 2, 4, 6, 8, 10, 12 and 14.
The ZL30226 has links 0, 4, 8, and 12.
Note: For ZL30226 groups 0, 1, 2 and 3 should be used.
7.1
0x0008-0x000B
0x0048-0x004B
0x0000-0x0007
0x0040-0x0047
Address
0x0010
0x0012
0x0050
0x0051
SRAM decoding for ZL30226 and ZL30227
Register Summary
0x0011
(Hex)
Register Descriptions
Access
Type
D
D
D
D
D
D
D
D
D
X0000000000
Reset Value
00000
(Hex)
0000
0000
0000
0000
0000
0000
0000
0000
Table 5 - Register Summary
Zarlink Semiconductor Inc.
ZL30226/7/8
UTOPIA Output Link Address Registers
UTOPIA Output Group Address Registers
UTOPIA Output Link PHY Enable Registers
UTOPIA Output Group PHY Enable Register
UTOPIA Output User Defined Byte
UTOPIA Input Link Address Registers
UTOPIA Input Group Address Registers
UTOPIA Input Link PHY Enable Register
UTOPIA Input Group PHY Enable Register
69
Description
sr_cs_1
) to the normally
Data Sheet