ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 22

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

ZL30227 Pin Description (continued)
AD13
AE13
AC26
AE21
AE19
AD17
AA26
Pin #
AF21
AC25
W25
W24
AF19
AF17
AC9
M26
R23
U25
G25
U24
N24
G26
C23
C20
Y23
E26
A25
A22
B20
T26
F24
B22
L24
J23
L25
J25
TXCKio
RXCKi
Name
up_oe
up_irq
up_cs
up_rd
DSTo
DSTi
[14]
[12]
[10]
[14]
[12]
[10]
[14]
[12]
[10]
[14]
[12]
[10]
[8]
[6]
[4]
[2]
[0]
[8]
[6]
[4]
[2]
[0]
[8]
[6]
[4]
[2]
[8]
[6]
[4]
[2]
[0]
or
[0
I/O
I/O TDM Interface Transmit Clock. This pin is an input or an output as selected
O Processor Interrupt Request. Open drain signal. If this signal is low, the
O Serial TDM Data Output. Serial stream which contains transmit data. The
I
I
I
I
Output enable (Motorola Mode). This is an input signal. This signal should be
tied to GND for Motorola timing mode.
Processor Read (Intel Mode). This is an input signal, active low. If low, data is
read from the ZL30227.
Chip Select. This is an active low input signal. If this signal is high, the
ZL30227 ignores all other signals on its processor bus. If this signal is low, the
ZL30227 accepts the signals on its processor bus.
ZL30227 signals to the processor that an interrupt condition is pending inside
the ZL30227.
output is set to high impedance for unused time slots and if the link is not used.
It is aligned with TXCKio.
Serial TDM Data Input. Serial stream which contains receive data. It is aligned
with RXCKi. These pins have internal weak pull-downs.
by the TDM TX Link Control registers. The TXCK source is software
selectable and can be either one of the eight RXCK or one of the four REFCK
signals when defined as output. When defined as input, the proper clock signal
is provided to the input pin. The clock polarity is determined by the TDM TX
Link Control registers. These pins have internal weak pull-downs.
TDM Interface Receive Clock. This input line represents the clock for the
receive serial TDM data. The expected frequency value to be received at this
input clock is defined by the user through the RX Link TDM Control register.
These pins have internal weak pull-downs.
TDM Interface Signals
Zarlink Semiconductor Inc.
ZL30226/7/8
22
Description
Data Sheet