ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 27

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

ZL30228 Pin Description (continued)
AE7,AD7,AC7,
AE8,AD8,AF7,
AF5,AE5,AD5,
AE4,AF3,AD4,
D12,B12,A12,
C13,B13,A14,
B14,C14,A15,
B7,A7,D8,C8,
A10,C11,D11,
B11,A11,C12,
B8,D9,C9,B9
A9,C10,B10,
AE12,AC12,
AC11,AD11,
AF10,AE10,
AF11,AE11,
AD10,AF9,
AF6,AD6,
AE9,AD9
AE3,AF2
A16,B16
AD13
Pin #
AF12
B15
D15
L1,
L2,
L4,
L3,
K1
J3
sr_cs_1, 0
URxAddr
URxClav
up_r/w
Name
up_wr
up_oe
sr_we
[18:0]
[15:0]
up_rd
[11:0]
up_d
up_a
[4:0]
sr_d
[7:0]
sr_a
or
or
I/O
I/O Static Memory Data Bus. Data Bus to exchange data between the ZL30228
I/O Processor Data Bus. Data Bus to exchange data between the ZL30228 and
O Static Memory Address Bus. Address bus on the external static memory.
O Static Memory Read/Not Write. If low, data is written from the ZL30228 to
O Static Memory Chip Select Signal. Active low.
O UTOPIA Receive Cell Available Signal. For cell-level flow control in a MPHY
I
I
I
I
Receiver Static Memory Interface Signals
environment, URxClav is an active high tri-stateable signal from the ZL30228
to ATM LAYER device.
Receive Address. Five bit wide address bus driven from the ATM to PHY
device to select the appropriate PHY address. URxAddr[4] is the MSB.
and the external static memory. sr_d[7:0] has internal weak pull-downs.
the memory. If high, data is read from the memory to the ZL30228.
a local processor.
Processor Address Bus. Used to select the internal registers and memory
locations of the ZL30228.
Processor Read/Not Write. Motorola Mode. This is an input signal. If low,
data is written from the processor to the ZL30228. If high, data is read from
the ZL30228 to the processor.
Processor Not Write (Intel Mode). This is an input signal, active low. If low,
data is written from the processor to the ZL30228.
Output enable (Motorola Mode). This is an input signal. This signal should
be tied to GND for Motorola timing mode.
Processor Read (Intel Mode). This is an input signal, active low. If low, data
is read from the ZL30228.
Processor Interface Signals
Zarlink Semiconductor Inc.
ZL30226/7/8
27
Description
Data Sheet