ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 105

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Synchronized access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
15:12
Bit #
Bit #
Bit #
Bit #
15:8
15:4
15:8
7:0
7:0
11
3
2
1
0
Type
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
Table 84 - RX UTOPIA IMA Group FIFO Overflow IRQ Enable Register
Unused. Read all 0’s.
When set to 1, the corresponding bit in the Overflow Status register can generate an
interrupt. A value of 0 inhibits the generation of an interrupt. IMA Groups 7:0.
Unused. Read all 0’s
Set when the UTOPIA output clock is missing or too slow. This latched bit is cleared by
writing a 0.
Set when the UTOPIA input clock is missing or too slow. This latched bit is cleared by
writing a 0.
Overflow of 1 or more of the TX UTOPIA FIFO.
Set when there is no free cell in TX Cell RAM. This latched bit is cleared by writing a 0.
Unused. Read all 0’s.
Reserved. Write 0 for normal operation.
Unused. Read 0’s.
Each bit set to ’1’ will enable the generation of the interrupt when the corresponding bit in
the IRQ IMA Group Overflow Status register is set. There is one bit for each status bit.
0x040C (1 reg)
1 register to enable interrupts from IMA Groups. The RxClk signal must be active
for correct register operation.
0000
0x040E (1 reg)
0000
0x040F (1 reg)
0080
0x040B (1 reg)
1 register for all 8 status bits.
0000
Table 83 - IRQ IMA Group Overflow Enable Register
Table 86 - Counter Transfer Command Register
Table 85 - General Status Register
Zarlink Semiconductor Inc.
ZL30226/7/8
105
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