ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 21

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

ZL30227 Pin Description (continued)
A10,C11,D11,B
2,B12,A12,C13
11,A11,C12,D1
AE7,AD7,AC7,
AE8,AD8,AF7,
AE5,AD5,AE4,
AF3,AD4,AE3,
,B13,A14,B14,
AF6,AD6,AF5,
B7,A7,D8,C8,
C14,A15,B15
B8,D9,C9,B9
A9,C10,B10,
AE12,AC12,
AC11,AD11,
AF10,AE10,
AF11,AE11,
AD10,AF9,
AE9,AD9
A16,B16
Pin #
AF12
D15
AF2
L1,
L2,
L4,
L3,
K2
K1
J3
sr_cs_1, 0
URxAddr
URxClav
URxEnb
up_r/w
Name
up_wr
sr_we
[18:0]
[15:0]
[11:0]
up_d
up_a
[4:0]
sr_d
[7:0]
sr_a
or
I/O
I/O Static Memory Data Bus. Data Bus to exchange data between the ZL30227
I/O Processor Data Bus. Data Bus to exchange data between the ZL30227 and a
O UTOPIA Receive Cell Available Signal. For cell-level flow control in a MPHY
O Static Memory Address Bus. Address bus on the external static memory.
O Static Memory Read/Not Write. If low, data is written from the ZL30227 to the
O Static Memory Chip Select Signal. Active low.
I
I
I
I
Receiver Static Memory Interface Signals
UTOPIA Receive Data Enable. Active LOW signal asserted by the ATM layer
device to indicate that URxData[15:0] ([7:0]) and URxSOC will be sampled at
the end of the next cycle. In multiple PHY configurations, URxEnb is used to
tri-state URxData and URxSOC ZL30227 outputs. In this case, URxData and
URxSOC would be enabled only in cycles following those with URxEnb
asserted. In UTOPIA L1, URxEnb must not be tied low and must transition from
high (disabled) to low (enabled) to indicate the beginning of data transfer.
environment, URxClav is an active high tri-stateable signal from the ZL30227
to ATM LAYER device.
Receive Address. Five bit wide address bus driven from the ATM to PHY
device to select the appropriate PHY address. URxAddr[4] is the MSB.
and the external static memory. sr_d[7:0] has internal weak pull-downs.
memory. If high, data is read from the memory to the ZL30227.
local processor.
Processor Address Bus. Used to select the internal registers and memory
locations of the ZL30227.
Processor Read/Not Write. Motorola Mode. This is an input signal. If low,
data is written from the processor to the ZL30227. If high, data is read from the
ZL30227 to the processor.
Processor Not Write (Intel Mode). This is an input signal, active low. If low,
data is written from the processor to the ZL30227.
Processor Interface Signals
Zarlink Semiconductor Inc.
ZL30226/7/8
21
Description
Data Sheet