ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 57

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

ZL30226/7/8
Data Sheet
5.0
UTOPIA Interface Operation
The ZL30226/7/8 supports the UTOPIA L1 and L2 Mode, 8 or 16-bit wide bus, with odd/even parity, for cell level
handshake only. In 8-bit UTOPIA mode maximum supported clock is up to 52 MHz and in 16-bit mode it is
33 MHz. Each port can be assigned an address ranging from 0 to 30. The address value of 31 is reserved and should
not be used.
The TX and RX paths of each IMA Group and each link in TC has its own PHY address. These PHY addresses are
defined in the UTOPIA Input Link Address (0x0040-0x0047) registers, UTOPIA Input Group Address
(0x0048-0x004B) registers, UTOPIA Output Link Address (0x000-0x0007) registers, and the UTOPIA Output
Group Address (0x0008-0x000B) registers. The UTOPIA Input LINK PHY Enable (0x0050) and the UTOPIA
Output Link PHY Enable (0x0010) registers are used to enable the PHY Address of the links in TC mode. The
UTOPIA Input Group PHY Enable (0x0051) register and the UTOPIA Output Group PHY Enable (0x0011)
registers are used to enable the PHY Address of the IMA Groups.
The ZL30226/7/8 UTOPIA port uses handshaking signals to process data streams. The start of a cell (SOC) is
marked by the UTOPIA SOC sync signal. This signal is active during the transfer of the first byte/first word of a cell.
The 52 bytes/26 words that follow the arrival of the first byte/first word of a cell are interpreted as belonging to the
same cell and are stored accordingly.
The Cell Available status line (Clav) is used to communicate to the ATM controller whether the ZL30226/7/8 has
space for a cell in the PHY address that was polled in the previous cycle. Whenever there is space for a cell in the
TX direction or a cell ready in the RX direction, the TXClav and/or RXClav signal will be driven High. If there is no
space in Tx direction and/or no cell is ready in Rx direction, the TxClav and/or RxCLav will be kept low.When the
address does not correspond to any enabled PHY address inside the ZL30226/7/8, the TXClav and RXClav signal
are set to High impedance mode. The use of an external pull-down may be required for the proper operation of the
Utopia bus in MPHY mode.
Note that the transmit or receive Utopia clock frequencies do not have to be synchronized with the system clock by
their frequencies cannot exceed the system clock frequency.
Important Note: The ZL30226/7/8 doesn’t support the back-to-back mode on Rx side(ATM output port). Depending
on which ATM controller the ZL30226/7/8 interfaces to, there might be interoperability issues that affect the receive
side communication. For details, please refer to Technical Note ZLAN-88: UTOPIA Interface between MT90224/3/2
and Specific ATM Controllers. This application note is covering the ZL30226/7/8 as well.
5.1
ATM Input Port
The UTOPIA interface input clock TxClk is independent of the system clock. The UTOPIA TxClk can be up to 52 MHz
for 8-bit mode and up to 33 MHz for 16-bit mode. The incoming cell is stored directly in the internal TX Cell RAM
where the TX UTOPIA FIFOs are implemented.
The UTOPIA transmit clock (TxClk) is checked against the system clock. If the incoming byte clock frequency is
lower than 1/128 of the system clock, bit 2 of the General Status (0x040E) register will be set. This bit is cleared by
overwriting it with 0. This aids in debugging as the presence of a UTOPIA clock is required not only for data
transfer but also for proper operation of the UTOPIA registers.
The total space for the UTOPIA input cells for all IMA Groups and links in TC mode is 118. These 118 cells are
shared between 24 TX UTOPIA FIFOs and 16 TX Link FIFOs. The size (length) of each TX UTOPIA FIFO is defined
by writing to the TX IMA Group FIFO Length Definition (0x0093 - 0x0096) registers. The maximum value is 6 and
the minimum value is 0 (in the case the PHY port is not to be used). The size of the TX Link FIFO is defined on a per
group using the TX IMA Control (0x0321-0x0324) registers.
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Zarlink Semiconductor Inc.