ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 67

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

6.3.2
Direct access registers can be written or read directly by the microprocessor, without having to use other registers.
Upon a write access to the ZL30226/7/8 internal registers, the data is stored in an internal latch and transferred to
the destination register within 2.5 system clock cycles (50 nsec at 50 MHz). No specific action is required if the
microprocessor provides at least 50 nsec (with Chip Select signal inactive) between 2 consecutive write accesses
or between a write and a read back of the same register. If the microprocessor is faster, then consecutive accesses
must be inhibited or wait state(s) introduced (this option is available on most MCUs).
6.3.3
Indirect access registers cannot be accessed directly by the microprocessor. The value is transferred back and forth
using registers which hold a copy of the information (data) and internal address of the register. This is required to
stabilize the read value. Consider for example the transfer of a TX ICP cell that requires almost 200 system clock
cycles. A dedicated ready bit which can optionally generate an interrupt is implemented for this type of transfer.
Accessing any of the 24-bit counters provides another example. A ready bit is implemented in the Counter Transfer
Command register when the transfer is completed.
When accessing indirect registers specified by the RX Delay Select (0x02AA) or RX Delay Link Number (0x0286)
registers, the value in the indirect registers can be read when the write to the selection register is effectively done
(i.e., 2.5 system clock cycles after the write cycle is completed). There is no additional delay required.
6.3.4
The status bits will remain set until cleared by a specific write action from the microprocessor. Status bits are cleared
by overwriting a zero to the corresponding position in the source register. Each input status register has a related
interrupt enable register. When enabled, setting a bit in the interrupt enable register causes an interrupt to occur in
the corresponding status register bit.
6.3.4.1
Some registers include a toggle bit. Toggle bits are used to indicate a write action to any internal register has taken
place. Typically, this bit is toggled 2.5 system clock cycles after performing the write action. To use the toggle bit, its
state (either 0 or 1) must be read (polled) and its state is changed (toggled) when a write command is completed.
This bit is particularly useful when the processor clock is much faster than the ZL30226/7/8 system clock.
6.4
The ICP Cell is used in the IMA protocol to exchange information to maintain proper operation between the Far End
and the Near End of the IMA group. One byte, the SCI byte, is used to indicate when there is new information to be
processed in the incoming ICP cell and it is monitored by the IMA software to determine when to process an incoming
ICP cell. In the normal mode of operation, the SCCI byte is monitored and an interrupt is generated whenever the
value of the byte had changed. The software has to read most of the bytes of the new ICP cell to determine which
bytes had changed and take appropriate action.
To simplify the monitoring process of the ICP cell, the ZL30226/7/8 includes an option to compare, on a per byte by
byte basis, the most recent incoming cell placed in the RX ICP Cell buffer with the previous cell written in the same
buffer. The cells that are placed in the RX cell buffer are selected based on the criteria specified in the RX Cell Type
RAM (0x0100-0x0101) registers. Another option can be selected where bytes 8, 52 and 53 are not compared and
are not reported. Byte 8 contains the IMA Frame Sequence number. It is used for the IMA Frame State Machine and
is not used by the Link or Group State Machines. Bytes 52 and 53 contain the CRC-10 and are not required by the
user. The RX Cell Processor can be enabled on a per link basis.
Cell Preprocessor Block
Direct Access
Indirect Access
Clearing of Status Bits
Toggle Bit
Zarlink Semiconductor Inc.
ZL30226/7/8
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Data Sheet