ZL30226/GA ZARLINK [Zarlink Semiconductor Inc], ZL30226/GA Datasheet - Page 115

• Manufacturer Part Number: ZL30226/GA
• Description: 4/8/16 Port IMA/TC PHY Device for xDSL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
15:12
Bit #
Bit #
15:5
6:5
4:3
4:0
10
11
9
8
7
2
1
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R
Unused. Read 0’s.
Reserved. Write 0 for normal operation.
Automatic ATM cell synchronization
Write 1 for normal operation. Register 0x0741 must also be initialized.
Reserved. Write 0 for normal operation.
Digital Loopback mode
When 1, loopback mode, RXCK and DSTi come from the TX pins of the same link. Both
TX and RX blocks operate normally.
When 0, normal mode, RXCK and DSTi come from the RX pins of the link
Link enable:
0: RX Port is not active
1: RX port is active
Data rate: Bits 4:3 must be 00
11:
10:
01:
00:
Reserved.
Write 00 for normal operation.
Reserved.
Write 0 for normal operation.
Clock polarity:
When 0, the data is sampled at the rising edge of RXCK
When 1, the data is sampled at the falling edge of RXCK
Unused. Read all 0’s.
These 5 bits are used to select the source for the signal at PLLREF0:
The valid combinations are:
00000: RXCK0 01000: RXCK8
00001: RXCK1 01001: RXCK9
00010: RXCK2 01010: RXCK10
00011: RXCK3 01011: RXCK11
00100: RXCK4 01100: RXCK12
00101: RXCK5 01101: RXCK13
00110: RXCK6 01110: RXCK14
00111: RXCK7 01111: RXCK15
0x0700 - 0x070F (16 reg)
1 reg. per RX link.
0000
0x0634- 0x0635 (2 reg)
0000
10.0 Mb/sec. (Only link 0, 4, 8 and 12 can be used)
5.0
2.5
Table 105 - PLL Reference Control Register
Table 106 - TDM RX Link Control Register
Reserved
Mb/sec. (Only links 0, 2, 4, 6, 8, 10 and12 can be used)
Mb/sec (All links are available)
Zarlink Semiconductor Inc.
ZL30226/7/8
115
1xxxx: reserved
Description
Description
Data Sheet